Virtual memory address translation method based on memory mapping adjacency

Abstract

The invention discloses a virtual memory address translation method based on memory mapping adjacency. The virtual memory address translation method comprises the following steps: 1) dividing a virtual address space of each 2MB into eight memory sub-domains with equal length; 2) when the operating system allocates the memory space, scanning the page table, identifying continuously mapped memory sub-domains, and storing mapping continuity information in the memory sub-domains and between the memory sub-domains in unused bits in a second-level page table entry; (3) when the page table is searched in the address translation process, address translation information of the continuous mapping memory domain is merged according to mapping continuity information stored in the second-level page table entry and stored in the TLB; and 4) in order to further improve the page number of the combinable address translation information, detecting the continuity between the continuously mapped memory sub-domains while searching the page table, and storing the continuity information between the memory sub-domains in a memory sub-domain cache so as to reduce the memory access times. According to the method, the coverage area of the TLB can be effectively improved, the hit rate of the TLB is increased, and therefore the overhead of virtual memory address translation is reduced.

Description

technical field [0001] The invention relates to the fields of virtual memory management, address translation and the like, in particular to a virtual memory address translation method based on memory mapping adjacency. Background technique [0002] Virtual memory technology can effectively improve process security and available memory capacity. Before virtual memory-based memory access, virtual addresses need to be translated into physical addresses, and then physical addresses can be used to access memory data. In a structure with 4-level page tables, since the page tables are stored in memory, the address translation process needs to access the memory up to 4 times, which is very time-consuming. For a long time, address translation operations have been considered to be one of the performance bottlenecks of processors. Although the translation lookaside buffer (TLB for short) can avoid multiple memory accesses caused by the page table query operation to a certain extent, a...

AI Technical Summary

Problems solved by technology

However, the current address translation merging method based on base pages can only combine address translation information of a limited number of base pages. In order to combine address translation information of as many base pages as possible, it is necessary to change the memory management strategy of the operating system to allocate as much as possible Large contiguous mapped memory domain

[0008] To sum up, it can be seen that in order to improve the efficiency of address translation, the existing methods either need the support of huge pages, or need to modify the memory management mechanism of the operating system

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