An on-chip soft start circuit for dc-dc switching power supply chip
A switching power supply chip, soft-start circuit technology, applied in electrical components, output power conversion devices and other directions, can solve the problem of soft-start circuit conversion efficiency and other performance can not meet the use requirements and other problems, to improve conversion efficiency and circuit performance, save money Chip area, effect of eliminating voltage and current spikes
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Embodiment 1
[0052] See figure 1 , figure 1It is a schematic structural diagram of an on-chip soft-start circuit for a DC-DC switching power supply chip provided by an embodiment of the present invention, including:
[0053] Slope voltage generating module 1, used to generate a reference voltage signal;
[0054] A control voltage generation module 2, connected to the slope voltage generation module 1, for generating a control signal according to the reference voltage signal;
[0055] The power tube grid width modulation module 3 is connected to the control voltage generation module 2 and is used to control the power tube to be turned on and off according to the control signal, and to feedback and adjust the control signal.
[0056] In this embodiment, the slope voltage generation module 1 includes: a slope voltage generation unit 11 for generating a slope signal; a voltage selection unit 12, one end of which is connected to the slope voltage generation unit 11, and the other end is conne...
Embodiment 2
[0109] The soft start process of the present invention will be further described through simulation experiments below.
[0110] See Figure 9 , Figure 9 is the simulation waveform diagram of the slope voltage generation circuit provided by the embodiment of the present invention; in the soft start process, SS and the bandgap reference voltage V REF comparison, since SS is less than V REF , so SS_OUT remains low, and the SS signal is sent to Vref; when the soft-start process ends, SS_OUT outputs high, and V REF sent to Vref, so that under the control of SS_OUT, the SS and V REF The selection of the final reference voltage Vref signal starts as a ramp up, and then remains at V REF Waveforms with constant values, such as Figure 9 shown.
[0111] See Figure 10 , Figure 10 It is the simulation waveform diagram of the n=4 hour delay signal generating circuit provided by the embodiment of the present invention; from Figure 10 It can be seen from the figure that the outp...
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