Chip verification auxiliary environment and chip verification system

Abstract

The invention discloses a chip verification auxiliary environment and a chip verification system. The chip verification auxiliary environment comprises an application scene database used for recordingall application scenes of a chip; a verification scene generation and conversion unit used for automatically generating various to-be-verified verification scenes according to the application scenesand converting formats of all configurations of the verification scenes into languages which can be recognized by the verification environment; a data acquisition and analysis processing unit used for generating a random seed and acquiring a verification result of a verification scene in the verification environment; a scene configuration unit which selects a verification scene according to the random seed, and sends each configuration of the verification scene to the verification environment for verification of the verification scene. According to an auxiliary environment, all verificationscenes can be automatically generated according to settings and converted into languages which can be recognized by the verification environment; the verification environment setting accuracy and thechip verification speed are greatly improved, and the chip development progress is accelerated.

Description

technical field [0001] The invention relates to the field of chip verification, in particular to a chip verification auxiliary environment and a chip verification system. Background technique [0002] Chip verification refers to the full verification of its hardware and software before chip tape-out, so that some defects that are difficult to find in the chip design process can be found in time, and timely adjustments and iterations can be made to ensure the smooth progress of tape-out. In contemporary complex chips In chip design, 50% to 80% of the work is in verification, so verification determines the efficiency of the entire design process in chip design. [0003] As the integration scale and complexity of chips become higher and higher, chip verification becomes more and more important. During the verification process, thousands of verification tasks of different scales are often faced at the same time. How to quickly and effectively conduct chip verification has becom...

AI Technical Summary

Problems solved by technology

[0004] In the existing technology, chip verification generally only focuses on whether the single configuration of the application scenario is covered, and generally ignores the combined application scenarios between configurations and configurations. It depends entirely on the randomization of the configuration of the environment, which requires random The number of times is very large, and not all scenarios can be verified

[0005] In the prior art, there are also combination scenarios between configurations and configurations, which are also verified in a random way, and some combination scenarios may not be verified; for example, the verification of a chip includes 4 configurations A / B / C / D verification, in the existing verification environment, there are more than 100 or more application scenarios for the above four configurations of A / B / C / D combinations, and it may take 500 random times or more to be able to verify all Combinations are all verified, and because they are all random combinations, it is also possible that some application scenarios of configuration combinations have not been verified, resulting in incomplete verification; and there is no dedicated environment in the prior art to count whether all application scenarios are able to cover

[0006] In addition, in the prior art, if it is necessary to count all the verification scenarios (including various combination application scenarios), manual statistics are required, the workload is heavy, the time is long, and it is easy to make mistakes, so that the traditional chip simulation verification method has time-consuming long, low degree of automation, time-consuming and labor-intensive, and error-prone personnel verification, which leads to a longer development cycle of the entire chip

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