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Forming method of semiconductor structure

A semiconductor and conductive unit technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, electrical components, etc.

Inactive Publication Date: 2020-02-11
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However shrinking size often presents new challenges such as isolation, leakage current, reliability, parasitic series resistance, and parasitic coupling resistance

Method used

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  • Forming method of semiconductor structure
  • Forming method of semiconductor structure
  • Forming method of semiconductor structure

Examples

Experimental program
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Effect test

Embodiment Construction

[0049] Different embodiments or examples provided below may implement different structures of the present disclosure. The following examples of specific components and arrangements are used to simplify the present disclosure and not to limit the present disclosure. For example, a description of forming a first component on a second component includes an embodiment in which the two are in direct contact, or an embodiment in which the two are interposed by other additional components rather than in direct contact. On the other hand, multiple examples of the present disclosure may repeatedly use the same reference numerals for brevity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0050] In addition, a structure of an embodiment of the present disclosure may be formed on, connected to, and / or coupled into another structure, the structure may directly contact the other structu...

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PUM

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Abstract

The invention provides a forming method of a semiconductor structure. The disclosure provides an intermetal dielectric layer in an multilevel interconnect system, and discloses a method to form low-kdielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described includePECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and O2 gas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where O2 gas may be used and, along with the O2 gas, precursors containing embedded Si-O-Si bonds, such as (CH3O)3-Si-O-Si-(CH3O)3) and (CH3)3-Si-O-Si-(CH3)3 may be used.

Description

technical field [0001] Embodiments of the present disclosure relate to an interconnection structure, and more particularly to the composition and method of forming an IMD layer. Background technique [0002] The semiconductor industry continues to innovate semiconductor technologies, such as multiple patterning to reduce the minimum size of structures (such as lines, spaces, and holes), three-dimensional transistors (such as fin field effect transistors), more interconnect layers, and buried in semiconductor Electronic components in an interconnection system stacked on a substrate to increase the integration of electronic components (such as transistors, diodes, resistors, capacitors, or the like) with interconnection structures (such as contacts, vias, lines, joints, etc.) in integrated circuits pad, or similar) density. Reducing size increases the inherent speed of electronic components, and higher integrated circuit functionality can be implemented for any given cost. H...

Claims

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Application Information

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IPC IPC(8): H01L21/8234
CPCH01L21/823431H01L21/823475H01L21/02126H01L21/02216H01L21/02274H01L21/76801H01L21/76804H01L21/76825H01L23/5329H01L23/53295H01L21/02164H01L21/02205H01L21/02211H01L21/0228H01L21/76802H01L21/76877
Inventor 刘中伟柯宇伦邱意为
Owner TAIWAN SEMICON MFG CO LTD