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FPGA encryption method and device based on MD5 algorithm

A technology of encryption device and encryption method, which is applied in the direction of encryption device with shift register/memory, secure communication device, internal/peripheral computer component protection, etc., to achieve the effect of convenient protection and quick judgment

Inactive Publication Date: 2020-02-11
西安极光航空航天科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is currently no convenient way to control the scope of use of the FPGA, and at the same time quickly determine the software version inside the FPGA

Method used

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  • FPGA encryption method and device based on MD5 algorithm
  • FPGA encryption method and device based on MD5 algorithm
  • FPGA encryption method and device based on MD5 algorithm

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0056] A simple example is given here to illustrate the relationship between the initialized data, the four original data and the calculated data. Firstly, the original data is given as 512'h{32'h0,32'h8,416'h0,32'h8061}, and then four original data are given as A=32'h67452301, B=32'hefcdab89, C= 32'h98badcfe and D=32'h10325476. Using formulas (1) (2) (3) (4) and (5) to jointly calculate the final check value of 128'h0CC175B9C0F1B6A831C399E269772661. Use the serial port to send the packet header format and checksum data as shown in the table in appendix b to check whether the FPGA chip selection signal is normally enabled; use the serial port to send the packet header format and other data as shown in the table in appendix b to check whether the FPGA chip selection signal cannot be opened normally .

Embodiment 2

[0058] A simple example is given here to illustrate the relationship between the initialized data, the four original data and the calculated data. Firstly, the original data is 512'h{32'h0, 32'h8, 416'h0, 32'h 8061}, and then the four original data are A=32'h00000618, B=32'hefcdab89, C =32'h98badcfe and D=32'h10325476. Using formulas (1) (2) (3) (4) and (5) to jointly calculate the final check value is 128'hB95480924BD2716EF377DF8350D529B2. Use the serial port to send the packet header format and checksum data as shown in the table in appendix b to check whether the FPGA chip selection signal is normally enabled; use the serial port to send the packet header format and other data as shown in the table in appendix b to check whether the FPGA chip selection signal cannot be opened normally . It can be seen from the comparison between Embodiment 1 and Embodiment 2 that two completely irrelevant checksums can be obtained only by changing A in the four initial data.

[0059] app...

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Abstract

The invention relates to an FPGA encryption method and device based on an MD5 algorithm. The method comprises the following steps: establishing initialization data; calculating a check sum array according to the initialization data and an MD5 message digest algorithm; obtaining a checksum of the FPGA; comparing the checksum array with the checksum of the FPGA, and if the checksum array is consistent with the checksum of the FPGA, enabling the FPGA to enter a normal working state; and if not, enabling the FPGA to enter an idle state. The encryption device comprises: an establishing unit used for establishing initialization data; a calculation unit which is used for calculating a check sum array according to the initialization data and the MD5 message digest algorithm established by the establishment unit; an acquisition unit which is used for acquiring an FPGA checksum; a comparison unit which is used for comparing the check sum array calculated by the calculation unit with the FPGA check sum acquired by the acquisition unit. If the checksum array is consistent with the checksum of the FPGA, the FPGA enters a normal working state; if the checksum array is inconsistent with the checksum of the FPGA, the FPGA enters an idle state; the FPGA checksum is obtained in a serial port communication mode. The method has the advantages that intellectual property protection, version management and control and use range management and control of the programmable logic device can be realized.

Description

technical field [0001] The invention belongs to the field of encryption and decryption of FPGA data streams, and in particular relates to an FPGA encryption method and device based on an MD5 algorithm. Background technique [0002] In the self-developed programmable logic (FPGA) project, it is necessary to control the quantity and scope of use of programmable logic. Here, it is necessary to encrypt the programmable logic to achieve effective control of the intellectual property rights in the programmable logic; The FPGA is encrypted to verify the correctness of the logic version and to control the use of the FPGA. However, there is currently no convenient way to control the scope of use of the FPGA, and at the same time quickly determine the software version inside the FPGA. The technical solution of the present invention aims to solve the above problems. [0003] The existing Chinese patent document CN201910364922.3 discloses a device and method for decrypting an FPGA enc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L9/32H04L9/18G06F21/72
CPCH04L9/3239H04L9/065G06F21/72
Inventor 吴小光李威力
Owner 西安极光航空航天科技有限公司