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Write-back circuit and method for improving reading stability of sensitive amplifier

A sensitive amplifier and stability technology, which is applied in the field of write-back circuit to improve the reading stability of the sensitive amplifier, can solve problems such as data loss, and achieve the effect of improving reliability and reading stability

Active Publication Date: 2020-02-21
XI AN UNIIC SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] In order to solve the problem of data loss during the existing read operation data amplification process, the present invention provides a write-back circuit and method for improving the read stability of the sense amplifier, and writes back the signal MA / MA_N amplified by the second-stage sense amplifier to the first-stage sense amplifier. In a first-stage sense amplifier

Method used

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  • Write-back circuit and method for improving reading stability of sensitive amplifier
  • Write-back circuit and method for improving reading stability of sensitive amplifier
  • Write-back circuit and method for improving reading stability of sensitive amplifier

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Embodiment 1

[0061] see figure 2 as shown, figure 2 A write-back circuit for improving the read stability of the sense amplifier of the present invention includes a first-stage sense amplifier, and the NMOS transistor N10 and the NMOS transistor N11 are connected to the first-stage sense amplifier and the main DQ read control circuit; the precharge PMOS transistor P10 and the PMOS The transistor P11 and the balance PMOS transistor P12 form the pre-charging circuit of the main DQ, and the transmission tube M0 and the transmission tube M1 are connected to the main DQ read control circuit and the second-stage sense amplifier.

[0062] The power supply of the first-stage sense amplifier is connected to VBLH, the sources of the NMOS transistor N10 and the NMOS transistor N11 are respectively connected to the bit line BL and the bit line inversion signal BL_N, and the gates of the NMOS transistor N10 and the NMOS transistor N11 are connected to the column selection line CSL signal, The drains...

Embodiment 2

[0070] image 3 Shown is the schematic of the second write-back circuit to improve the read stability of the sense amplifier. Including the first-stage sense amplifier, the NMOS transistor N10 and NMOS transistor N11 are connected to the first-stage sense amplifier and the main DQ read control circuit; the pre-charge PMOS transistor P10, PMOS transistor P11 and equalization PMOS transistor P12 form the pre-charge circuit of the main DQ, thick The gate NMOS transistor HN0 and the transistor HN1 are connected to the main DQ and the second-stage sense amplifier.

[0071] The power supply of the first-stage sense amplifier is connected to VBLH, the sources of NMOS transistor N10 and NMOS transistor N11 are connected to the bit line BL and the bit line inverse signal BL_N, the gates of N10 and N11 are connected to the column selection line CSL signal, and the drains of N10 and N11 The poles are respectively connected to the amplification lines MDQ / MDQ_N.

[0072] The gates of the...

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Abstract

The invention discloses a write-back circuit and method for improving the reading stability of a sense amplifier, and the circuit comprises a first-stage sensitive amplifier which carries out the first amplification of data, and transmits the amplified data to an amplification line; a second-stage sensitive amplifier which is used for carrying out secondary amplification on the amplified data; a main DQ read control circuit which is connected with the first-stage sensitive amplifier and the second-stage sensitive amplifier and is kept on, is used for transmitting the amplified data to the second-stage sensitive amplifier, and writing the data subjected to secondary amplification back to the amplification line so as to write back to the first-stage sensitive amplifier, and recovering a voltage peak coupled to a bit line BL or BL_N of the first-stage sensitive amplifier. According to the write-back circuit for improving the reading stability of the sense amplifier, a signal MA / MA _ N amplified by the second-stage sense amplifier is written back into the first-stage sensitive amplifier. The reading stability of the first-stage sensitive amplifier is improved, and the reliability of reading operation is improved.

Description

technical field [0001] The invention relates to the field of memory design, in particular to a write-back circuit and method for improving the read stability of a sense amplifier. Background technique [0002] Sensitive amplifiers are widely used in memory read operations, mainly for amplifying small signals on bit lines to digital signals. In the memory read operation stage, the first-stage sense amplifier amplifies the small signal read from the array. When the small signal is amplified to a recognizable digital signal, the main DQ (DQ, that is, Data I / O is the input and output line or connection of data Interface) The read control circuit transmits the amplified digital signal to the second-stage sense amplifier, and the signal is amplified twice by the second-stage sense amplifier. [0003] Such as figure 1 Shown is the schematic diagram of the traditional memory read operation data amplification circuit: the operating voltage of the first-stage sense amplifier is the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/06G11C7/08
CPCG11C7/062G11C7/08
Inventor 熊保玉张颖庞理
Owner XI AN UNIIC SEMICON CO LTD
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