Storage unit and multi-port static random access memory

Abstract

The embodiment of the invention provides a storage unit and a multi-port static random access memory, and relates to the technical field of semiconductors. According to the embodiment of the invention, a storage circuit and a plurality of write-in circuits are arranged in the storage unit; the storage circuit comprises a first storage module, a second storage module and a control module. The control module is connected with a power supply voltage end, a grounding end and the second storage module, each write-in circuit comprises a write-in module and a pull-down module, the write-in module isconnected with a word line, a bit line and the input end of the first storage module, and the pull-down module is connected with the word line, the grounding end and the control module. By removing inverters and the reverse bit lines BLBs in the write-in circuits, when write-in operation occurs, extra power consumption caused by signal inversion on the reverse bit lines BLBs is avoided, and powerconsumption caused by the write-in operation is reduced; and when the signal input by the word line is valid, the path between the output end of the second storage module and the grounding end is disconnected, so that the reliability of writing operation is improved, and the writing difficulty is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a storage unit and a multi-port static random access memory. Background technique [0002] SRAM (Static Random Access Memory, static random access memory), as an important type of IP (Intellectual Property, intellectual property) / macrocell, occupies an important position in integrated circuit design. With the continuous development and optimization of integrated circuit systems, The demand for the number of SRAM ports is gradually increasing, and multi-port SRAM provides important support for controllers, processors, etc. to store random / out-of-order instructions or data. [0003] like figure 1 As shown, each storage unit in the existing multi-port SRAM includes a storage circuit 11 and a plurality of write circuits 12, and the plurality of write circuits 12 include two N-type transistors (such as transistor M1 and transistor M2) and An inverter F1, the storage circuit 1...

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Problems solved by technology

[0004] However, when the write operation occurs, if the signal input by the bit line BL is reversed, the signals on all the inverted bit lines BLB connected to the bit line BL are reversed, because only one write circuit 12 can be used for one storage circuit at a time. 11 for data writing, therefore, only the signal on one inverted bit line BLB is validly inverted, and the signals on the remaining inverted bit lines BLB are invalid inverted, resulting in increased power consumption caused by the write operation

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