Storage unit and multi-port SRAM

Abstract

The embodiment of the invention provides a storage unit and a multi-port SRAM, which relate to the technical field of semiconductors. In the embodiment of the present invention, a storage circuit and a plurality of writing circuits are arranged in the storage unit, the storage circuit includes a first storage module, a second storage module and a control module, and the control module is connected to a power supply voltage terminal, a ground terminal and the second storage module, Each writing circuit includes a writing module and a pull-down module, the writing module is respectively connected with the word line, the bit line and the input terminal of the first storage module, and the pull-down module is connected with the word line, the ground terminal and the control module respectively. By removing the inverters and the reverse bit line BLB in multiple write circuits, when the write operation occurs, no additional power consumption will be generated due to the signal inversion on the reverse bit line BLB, reducing the power consumption caused by the write operation ; When the signal input on the word line is valid, disconnect the path between the output terminal of the second memory module and the ground terminal, so as to increase the reliability of the writing operation and reduce the difficulty of writing.

Description

technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a storage unit and a multi-port static random access memory. Background technique [0002] As an important type of IP (Intellectual Property, intellectual property) / macrocell, SRAM (Static Random Access Memory) occupies an important position in integrated circuit design. With the continuous development and optimization of integrated circuit systems, The number of SRAM ports is gradually increasing, and multi-port SRAM provides important support for controllers, processors, etc. to store random / out-of-order instructions or data. [0003] like figure 1 As shown, each memory cell in the existing multi-port SRAM includes a memory circuit 11 and a plurality of write circuits 12, and each of the plurality of write circuits 12 includes two N-type transistors (such as transistor M1 and transistor M2) and An inverter F1, the storage circuit 11 includes a first storage mod...

AI Technical Summary

Problems solved by technology

[0004] However, when the write operation occurs, if the signal input by the bit line BL is reversed, the signals on all the inverted bit lines BLB connected to the bit line BL are reversed, because only one write circuit 12 can be used for one storage circuit at a time. 11 for data writing, therefore, only the signal on one inverted bit line BLB is validly inverted, and the signals on the remaining inverted bit lines BLB are invalid inverted, resulting in increased power consumption caused by the write operation

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