Wafer level packaging method and packaging structure
A wafer-level packaging and packaging method technology, which is applied to semiconductor/solid-state device components, semiconductor devices, electrical components, etc., and can solve the problems of large volume and thickness, unstable performance, and integrated circuits being easily affected by external magnetic fields. , to avoid the influence of electrical properties, small volume and thickness
Active Publication Date: 2022-03-18
NINGBO SEMICON INT CORP
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Problems solved by technology
[0004] Integrated circuits are easily affected by external magnetic fields during use, resulting in unstable performance
In the prior art, the shielding structure is set in the integrated circuit to reduce the interference of the external magnetic field. However, the integrated circuit with shielding function has the problem of large volume and thickness.
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Embodiment Construction
[0030] It can be seen from the background technology that the integrated circuit has the problem of large volume and thickness. The reason is that in order to reduce the interference of the external magnetic field, a metal shell is assembled on the integrated circuit chip in the prior art to shield the external magnetic field. However, the There is still a certain gap between the metal shell and the integrated circuit chip, which leads to an increase in the volume and thickness of the integrated circuit.
[0031] In order to solve the technical problem, the present invention provides a wafer-level packaging method, including: forming a bonding structure, the bonding structure includes: a device wafer and a plurality of first chips bonded to the device wafer Conformally covering an insulating layer on the plurality of first chips and the device wafer where the first chips are exposed; conformally covering a shielding layer on the insulating layer; forming an encapsulation layer ...
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Abstract
The present invention provides a wafer-level packaging method and packaging structure. The packaging method includes: forming a bonding structure, and the bonding structure includes: a device wafer and a plurality of first chips bonded to the device wafer Conformally covering an insulating layer on the plurality of first chips and the device wafer where the first chips are exposed; conformally covering a shielding layer on the insulating layer; forming an encapsulation layer on the shielding layer. The wafer-level packaging structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and all exposed parts of the first chips on the device wafer; the shielding layer conformally covers the insulating layer; the encapsulation layer is located on the shielding layer. The present invention reduces the volume and thickness of the formed package structure.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a wafer-level packaging method and packaging structure. Background technique [0002] With the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease, and people's requirements for packaging technology of integrated circuits continue to increase accordingly. Existing packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), Three-dimensional Packaging (3D) and System in Package (System in Package, SiP) and so on. [0003] At present, in order to meet the goals of lower cost, more reliability, faster speed and higher density of integrated circuit packaging, the advanced packaging method mainly adopts Wafer Level Package System in Package (WLPSiP). Compared with traditional system packaging, wafer-level system packaging completes the packaging integration proc...
Claims
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IPC IPC(8): H01L21/56H01L23/552
CPCH01L21/56H01L23/552H01L23/522H01L2224/18
Inventor 罗海龙克里夫·德劳利
Owner NINGBO SEMICON INT CORP