Hardware logic design-oriented demand modeling and verification method

Abstract

The invention discloses a hardware logic design-oriented demand modeling and verification method, which comprises the following steps of: 1, obtaining function modules divided in a demand analysis stage, and filling codes of the function modules into a table of a corresponding style; step 2, analyzing the filled forms which describe Verilog HDL statements with different functions in multiple styles, and recording a nested relationship of the forms between the same modules and an instantiation relationship of ports between different modules; 3, carrying out grammar and logic review on the codes; 4, generating a document for storing time sequence running logic by the module code; step 5, calling the documents of the time sequence operation logic at different clock edges, and displaying specific positions of logic branches where codes are located at different clock edge moments by using a table; and step 6, performing integration operation on the code after the verification logic is correct, and generating a Verilog HDL code framework corresponding to table filling. According to the method, logic can be automatically verified in a simple form filling mode, and the effect of pre-verification is achieved.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit verification, in particular to a hardware logic design-oriented demand modeling and verification method. Background technique [0002] For increasingly complex integrated circuits, any small design errors may lead to paralysis of the circuit. Through the verification work, defects in the integrated circuit design process can be found, and the possibility of design errors can be reduced. At present, the verification of integrated circuits is mainly divided into formal verification and simulation verification. Formal verification uses mathematical theorems to verify the consistency of code functions in the integrated circuit design stage, and uses an exhaustive method to conduct a complete search for all possible results. Simulation verification needs to input the excitation signal into the system to be tested, and verify the correctness of the circuit function through the simulation fe...

AI Technical Summary

Problems solved by technology

[0004] This application aims at the defect that verification cannot be performed in the requirements analysis stage in the current integrated circuit design process, and provides a hardware logic design-oriented requirements modeling and verification method. This method can automatically complete the logic by simply filling the form. Verification, to achieve the effect of pre-verification

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