The invention discloses a hardware logic design-oriented 
demand modeling and 
verification method, which comprises the following steps of: 1, obtaining function modules divided in a 
demand analysis stage, and filling codes of the function modules into a table of a corresponding style; step 2, analyzing the filled forms which describe 
Verilog HDL statements with different functions in multiple styles, and recording a nested relationship of the forms between the same modules and an instantiation relationship of ports between different modules; 3, carrying out grammar and logic review on the codes; 4, generating a document for storing 
time sequence running logic by the module code; step 5, calling the documents of the 
time sequence operation logic at different 
clock edges, and displaying specific positions of logic branches where codes are located at different 
clock edge moments by using a table; and step 6, performing integration operation on the code after the 
verification logic is correct, and generating a 
Verilog HDL code framework corresponding to table filling. According to the method, logic can be automatically verified in a simple form filling mode, and the effect of pre-
verification is achieved.