dram yield analysis system

Abstract

The present invention relates to the field of integrated circuits, and provides a DRAM yield analysis system for analyzing electrical failure data of DRAM chips and obtaining possible failure causes. For at least one possible cause of failure, after the data input module obtains the electrical failure data of the DRAM chip, the graphic module can process the electrical failure data and mark it in a grid diagram, and the marked data can be analyzed by the analysis module The grid diagram is compared with the plurality of failure templates to obtain at least one failure template matching the marked grid diagram, so that a possible failure cause corresponding to the marked grid diagram can be obtained. Using the above-mentioned DRAM yield rate analysis system, the possible cause of failure can be obtained in time from the electrical failure data of the DRAM chip, which is conducive to quickly improving the yield rate of the DRAM chip.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a DRAM yield analysis system. Background technique [0002] In the modern integrated circuit manufacturing process, chip processing needs to go through a series of process links such as cleaning, film formation, etching, heat treatment, etc., and each process may introduce various defects. Damage due to device defects is extremely costly. Under such conditions, by testing the chips on the wafer, analyzing the cause of failure, and obtaining factors affecting the chip yield to reduce device defects, that is, yield analysis has become an important link in integrated circuit manufacturing. [0003] Taking Dynamic Random Access Memory (DRAM) as an example, a DRAM chip usually includes a plurality of memory cells arranged in an array, and the electrical failure of the DRAM chip can be known by testing the formed memory cell array. In order to further understand the cause of electr...

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Problems solved by technology

[0004] However, it is very time-consuming to adjust the test conditions in order to find out the specific cause of the failure or the analysis process of the possible process, and requires a high level of operator experience. Faced with a large amount of test data, it is difficult to obtain the analysis results in time, which also leads to a high yield rate. The overall efficiency of the analysis is low, which is not conducive to the improvement of the yield rate of DRAM chip products

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