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Metallization stack, method of making same, and electronic device including metallization stack

A metallization and metal layer technology, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as increased manufacturing costs, integrated circuit short circuit or open circuit faults, and achieve increased integration density, reduced line width or The effect of CD and interval

Active Publication Date: 2022-07-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, it is difficult to align the metal lines with the vias, which can lead to short or open failures in the integrated circuit (IC) and thus increase the manufacturing cost of the IC

Method used

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  • Metallization stack, method of making same, and electronic device including metallization stack
  • Metallization stack, method of making same, and electronic device including metallization stack
  • Metallization stack, method of making same, and electronic device including metallization stack

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Embodiment Construction

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0014] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not to scale, some details have been exaggerated for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and may vary in practice due to manufacturing tolerances or technical limitations, and those skilled in the art will Regions / layers with differen...

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Abstract

A metallization stack, a method of making the same, and an electronic device including the metallization stack are disclosed. According to an embodiment, the metallization stack may include at least one interconnect layer and at least one via layer alternately arranged on the substrate. At least one pair of adjacent interconnect and via layers in the metallization stack includes interconnect lines in the interconnect layer and vias in the via layer. The interconnect layer is closer to the substrate than the via layer. The peripheral sidewall of the via on at least a portion of the interconnect line does not extend beyond the peripheral sidewall of the at least one portion of the interconnect line.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and more particularly, to metallization stacks, methods of making same, and electronic devices including such metallization stacks. Background technique [0002] As semiconductor devices continue to be miniaturized, it becomes increasingly difficult to fabricate high-density interconnect structures due to the need for extremely fine metal lines (meaning small grain size, excessive barrier thickness and thus high resistance) and Very small line spacing (meaning misaligned, difficult to fill contact holes). Additionally, it is difficult to align the metal lines with the vias, which can lead to short or open failures in the integrated circuit (IC) and thus increase the manufacturing cost of the IC. SUMMARY OF THE INVENTION [0003] In view of this, it is an object of the present disclosure, at least in part, to provide a metallization stack, a method of manufacturing the same, and an electr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/48H01L21/768H01L23/485H01L21/60
CPCH01L23/481H01L21/76805H01L24/20H01L24/19H01L2224/0231H01L2224/02331H01L2224/02333H01L2224/02381H01L21/76885H01L21/7682H01L23/528H01L21/76816H01L21/76847H01L23/53242H01L21/76801H01L21/7685H01L23/5226H01L23/53209H01L23/53257H01L23/5329
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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