26 results about "Pore interconnectivity" patented technology

A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.

The invention relates to the technical field of biological ceramic materials, in particular to a zirconium oxide bone repair scaffold material with a porous interconnection structure and a preparation method of the zirconium oxide bone repair scaffold material. The invention aims to solve the problems of poor mechanical property and fragile interconnection structure of the existing stent under high porosity. The core preparation process comprises the following steps of: performing acetone steam annealing and pre-fusion on a double-particle-size microsphere template to form a stable interconnection window prototype; then, a continuous hole wall main body is constructed through vacuum impregnation of high-viscosity zirconium oxide slurry, and then secondary positioning reinforcement is conducted on the interconnected neck parts through low-viscosity nano zirconium oxide sol; finally, diluted bioactive glass sol is introduced to endow the surface with biological activity, and a final product is obtained through temperature-controlled degreasing and sintering. According to the method, the pore connectivity, the mechanical strength and the biological activity of the scaffold are synergistically optimized through template pre-fusion and partition sequential processes, and the method is suitable for repairing load-bearing bone defects.

A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.

A through silicon via interconnection structure and a method of forming same, and a quantum computing device are provided. The method includes: providing a silicon wafer, having a first surface and a second surface opposite to each other; forming, in the silicon wafer, a through silicon via penetrating through the silicon wafer in a direction from the first surface to the second surface of the silicon wafer; forming a groove communicating with the through silicon via in a target surface of the first surface and the second surface of the silicon wafer using a photolithography process; and forming a superconducting thin film in the groove and the through silicon via to obtain the through silicon via interconnection structure.

A device comprising a lid layer (104); an acoustic layer (101) coupled to the lid layer (107), wherein the acoustic layer (104) comprises: a piezoelectric layer (108); a dielectric layer (106); at least one material layer (109) located in the dielectric layer (106); and a plurality of interconnects (130) coupled to the piezoelectric layer (108); a cavity (120) located between the lid layer (104) and the piezoelectric layer (108); a substrate (104) coupled to the dielectric layer (108) of the acoustic layer (104); and at least one via interconnect (105) coupled to the piezoelectric layer (108) through the plurality of interconnects (105), wherein the at least one via interconnect (105) extends through the dielectric layer (108) and the substrate (104).

A method for fabricating a metal oxide layer involves providing a metallic nitride substrate and performing electrochemical oxidation of the metallic nitride substrate in either an acidic or basic environment to form the metal oxide layer. This electrochemical oxidation process is characterized by a gas-evolving reaction that results in the formation and escape of nitrogen gas from the forming metal oxide layer such that a mesoporous 3D interconnected metal oxide structure comprising a 3D network of interconnected pores is formed. This method enables the creation of metal oxide layers with specific properties suitable for various applications, including but not limited to, use in batteries, and as electrodes in molecular synthesis.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

The invention provides a TGV glass substrate and a limiting growth process thereof. The limited growth process comprises the following steps: providing a glass substrate, wherein the glass substrate is provided with a front surface and a back surface which are opposite to each other; a plurality of glass through holes are formed in the glass substrate; pressing a metal foil on the back surface of the glass substrate to form a limiting substrate of the glass through hole, then growing a metal column in the glass through hole in a limiting manner, and forming a metal layer on the front surface of the glass substrate. The metal foil is introduced as the back conductive layer of the glass substrate, and a deposition process of a TGV through hole PVD seed layer is abandoned, so that economy and efficiency are improved, single-sided filling of the glass through hole is realized, a subsequent electroplating process is simplified from double-sided electroplating to single-sided electroplating, technological parameter variables are reduced by the conversion, and the production cost is reduced. The production stability and yield are improved, the thickness uniformity of the electroplated metal layer is finally improved, and a strong guarantee is provided for obtaining a high-performance and high-reliability glass through hole interconnection structure.

The invention provides a detection method for an interconnection structure, and the method comprises the steps: providing a semiconductor substrate with a to-be-detected interconnection structure, and the interconnection structure comprises an interconnection layer and a through hole interconnection structure electrically connected below the interconnection layer; a grinding process is executed to sequentially remove the interconnection layer and the through hole interconnection structure of the lower part of the interconnection layer so as to expose the surface of the residual through hole interconnection structure; performing a heat treatment on the via interconnect structure to recrystallize and shrink it; electron beam defect scanning is carried out on the shrunk through hole interconnection structure to obtain a contrast image, if a dark voltage contrast image in the contrast image can be obtained, it is judged that the electrical property of the through hole interconnection structure corresponding to the dark voltage contrast image is abnormal, and if the dark voltage contrast image in the contrast image is not obtained, it is judged that the electrical property of the through hole interconnection structure is normal. According to the invention, the detection rate and the detection accuracy of the electrical abnormality of the through hole interconnection structure can be improved.

This invention relates to the field of bioceramic materials technology, specifically to a porous interconnected zirconia bone repair scaffold material and its preparation method. This invention aims to address the problems of poor mechanical properties and fragile interconnected structures in existing scaffolds under high porosity. The core preparation process includes: using a dual-size microsphere template, pre-fusion via acetone vapor annealing to form a stable interconnected window prototype; subsequently, constructing a continuous pore wall body by vacuum impregnation with high-viscosity zirconia slurry; then, using low-viscosity nano-zirconia sol for secondary positioning and reinforcement of the interconnected necks; finally, introducing diluted bioactive glass sol to impart surface bioactivity, followed by temperature-controlled degreasing and sintering to obtain the final product. This method, through template pre-fusion and a zoned sequential process, synergistically optimizes the scaffold's pore connectivity, mechanical strength, and bioactivity, making it suitable for the repair of weight-bearing bone defects.

The invention discloses a TSV solid-phase hole filling interconnection method and structure, and relates to the technical field of semiconductor packaging. The TSV solid-phase hole-filling interconnection method comprises the steps of S1, silicon through hole etching and deposition, S2, copper column insertion and fixation, S3, surface treatment and interconnection construction and S4, electrical testing and process feedback, a complex electroplating production line is abandoned, the through holes are filled through plastic deformation of the solid copper columns, the inherent hole and seam problems of an electroplating method are avoided, and the TSV solid-phase hole-filling interconnection method is suitable for large-scale production. The high-purity solid copper columns are high in mechanical strength and are tightly and mechanically interlocked with the inner walls of the through holes through plastic deformation, and the anti-fatigue capacity of the interconnection structure under the thermal cycle load is improved by combining the insulating layer and the barrier layer, so that reliable vertical interconnection is obtained, thermal expansion coefficient mismatch of copper and silicon is effectively avoided, and the reliability of the interconnection structure is improved. Stress is generated on the interface in the electroplating process and the subsequent thermal cycle.

A device comprising a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.

A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.

A package comprising a metallization portion; an integrated device coupled to the metallization portion; a substrate; a plurality of wire bonds coupled to the substrate and the metallization portion; and an encapsulation layer coupled to the metallization portion. The encapsulation layer at least partially encapsulates the integrated device, the plurality of wire bonds and the substrate. The integrated device comprises a plurality of through substrate via interconnects.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

A package, the package comprising an interposer, the interposer comprising: a silicon substrate, the silicon substrate comprising a porous portion; and a plurality of via interconnects extending through the porous portion of the silicon substrate. The package includes a first integrated device coupled to an interposer through a first plurality of solder interconnects.

A substrate, the substrate comprising: at least one dielectric layer; a semiconductor device includes at least one dielectric layer, and a plurality of interconnects at least partially located in the at least one dielectric layer, where the plurality of interconnects includes a plurality of via interconnects, and where the plurality of via interconnects includes a first via interconnect including a substantially vertical first via wall.

A device comprising a substrate, a first integrated device coupled to a first surface of the substrate, a second integrated device coupled to the first surface of the substrate, a first passive device coupled to a second surface of the substrate and a second passive device coupled to the second surface of the substrate. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a power interconnect. The power interconnect is configured to be electrically coupled to power. The first integrated device, the first passive device, the second integrated device and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects are configured to operate as an inductor, where the first plurality of interconnects include a via interconnect.

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

An antifuse structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line, and a conductive etch stop layer separating both the first metal line and the second metal line from an underlying layer, where a first portion of the conductive etch stop layer directly beneath the first metal line comprises a first extension region and a second portion of the conductive etch stop layer directly beneath the second metal line comprises a second extension region opposite the first extension region.

The invention discloses a manufacturing method of a through hole interconnection outer layer partition, which comprises the following steps of: providing a production plate, arranging drilling positions on the production plate, and arranging at least two isolation discs on an inner layer hole ring corresponding to the drilling positions; through holes are drilled in the positions, corresponding to the drilling positions, of the production board, and then the isolation discs in the holes are removed through concave etching; metallizing the through hole through copper deposition and pulse electroplating to form a conducting hole with an internal partition, and at least one end of the conducting hole being a disconnected end; the via holes are plugged with resin and cured, and the resin protruding out of the plate surface is ground to be flat through a grinding plate; and manufacturing an outer layer circuit on the production board, and etching the hole wall copper layer at the break end of the via hole during etching so as to break the connection between the copper in the hole and the outer layer. According to the method, the purpose of isolating the inner layer and the outer layer of the through hole is achieved by etching a part of the hole wall copper layer at the broken end and filling the solder resist ink or the resin ink, and the space occupation of the outer layer through hole is effectively reduced.

A package comprising a metallization portion; an integrated device coupled to the metallization portion; a substrate; a plurality of wire bonds coupled to the substrate and the metallization portion; and an encapsulation layer coupled to the metallization portion. The encapsulation layer at least partially encapsulates the integrated device, the plurality of wire bonds and the substrate. The integrated device comprises a plurality of through substrate via interconnects.

According to the various aspects, a present device may include a plurality of through hole via interconnects that are made of at least two conductive materials, which includes a conformally plated cooper layer enclosing a plug / filling of a low modulus conductive epoxy composite material to form dual material interconnects. The present dual material interconnects may reduce thermally-induced stresses on a glass substrate, as compared with the materials used in conventional through hole via interconnects.

This invention provides a method for preparing porous interconnected hollow carbon nanofiber membranes, belonging to the field of nanomaterial preparation technology. The method first uses a mixture of MOF and a polymer as a shell precursor solution, and SAN resin or PMMA as a core layer precursor solution. A mixed matrix membrane material is prepared through coaxial electrospinning and subsequent carbonization. In the mixed matrix membrane, the SAN resin or PMMA acts as a self-sacrificial template, undergoing carbonization and volatilization to induce the formation of hollow carbon nanofibers. Meanwhile, the MOF induces the formation of porous structures on the hollow carbon nanofibers through interfaces, interconnecting them via hollow channels. This method is simple to operate, streamlined, and can be mass-produced, possessing significant practical application value in the fields of energy catalysis and environmental protection.