50 results about "Pore interconnectivity" patented technology

A method of making an interconnect substrate includes forming a first insulating layer containing a filler and covering a first interconnect layer, forming a via hole in the first insulating layer by laser processing, the via hole exposing the first interconnect layer, performing a heat treatment, plasma processing, and a desmear process in this order with respect to the first insulating layer, and forming, after the desmear process, a second interconnect layer including both an interconnect pattern formed on an upper surface of the first insulating layer and a via interconnect formed in the via hole.

The invention relates to the technical field of biological ceramic materials, in particular to a zirconium oxide bone repair scaffold material with a porous interconnection structure and a preparation method of the zirconium oxide bone repair scaffold material. The invention aims to solve the problems of poor mechanical property and fragile interconnection structure of the existing stent under high porosity. The core preparation process comprises the following steps of: performing acetone steam annealing and pre-fusion on a double-particle-size microsphere template to form a stable interconnection window prototype; then, a continuous hole wall main body is constructed through vacuum impregnation of high-viscosity zirconium oxide slurry, and then secondary positioning reinforcement is conducted on the interconnected neck parts through low-viscosity nano zirconium oxide sol; finally, diluted bioactive glass sol is introduced to endow the surface with biological activity, and a final product is obtained through temperature-controlled degreasing and sintering. According to the method, the pore connectivity, the mechanical strength and the biological activity of the scaffold are synergistically optimized through template pre-fusion and partition sequential processes, and the method is suitable for repairing load-bearing bone defects.

A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.

Techniques are provided herein for forming a via with an asymmetrically flared profile within the interconnect region over semiconductor devices. In some examples, a via within the interconnect layer has a greater critical dimension (CD), or top surface width, along a first direction (e.g., along an X-axis) than it has along a second direction orthogonal to the first direction (e.g., along a Y-axis). The bottom surface of the via may have substantially the same width along both the first and second directions, such that the width of the via tapers or steps inward between the top surface width along the first direction and the bottom surface width along the first direction. There is little to no tapering or step of the via between the top surface width along the second direction and the bottom surface width along the second direction.

The invention relates to a through hole structure and a manufacturing method thereof, and a manufacturing method of a through hole interconnection structure, and the manufacturing method of the through hole structure comprises the steps: forming a blind hole in a substrate; completely oxidizing the residual substrate material at the bottom of the blind hole; and removing the oxide layer to obtain a through hole structure which is provided with a through hole penetrating through the substrate. According to the method, the blind hole is formed in the substrate, a supporting sheet is not used for manufacturing the through hole structure, bonding and de-bonding equipment is not needed, and the production cost is saved. The substrate material with the residual thickness at the bottom of the blind hole is completely oxidized into the oxide layer through oxidation, and then the oxide layer is removed to obtain the through hole penetrating through the substrate, so that the back surface of the substrate does not need to be thinned, the defects of silicon slag and edge breakage caused by thinning are avoided, and the yield and the reliability of the device are improved.

A through silicon via interconnection structure and a method of forming same, and a quantum computing device are provided. The method includes: providing a silicon wafer, having a first surface and a second surface opposite to each other; forming, in the silicon wafer, a through silicon via penetrating through the silicon wafer in a direction from the first surface to the second surface of the silicon wafer; forming a groove communicating with the through silicon via in a target surface of the first surface and the second surface of the silicon wafer using a photolithography process; and forming a superconducting thin film in the groove and the through silicon via to obtain the through silicon via interconnection structure.

A device comprising a lid layer (104); an acoustic layer (101) coupled to the lid layer (107), wherein the acoustic layer (104) comprises: a piezoelectric layer (108); a dielectric layer (106); at least one material layer (109) located in the dielectric layer (106); and a plurality of interconnects (130) coupled to the piezoelectric layer (108); a cavity (120) located between the lid layer (104) and the piezoelectric layer (108); a substrate (104) coupled to the dielectric layer (108) of the acoustic layer (104); and at least one via interconnect (105) coupled to the piezoelectric layer (108) through the plurality of interconnects (105), wherein the at least one via interconnect (105) extends through the dielectric layer (108) and the substrate (104).

A method for fabricating a metal oxide layer involves providing a metallic nitride substrate and performing electrochemical oxidation of the metallic nitride substrate in either an acidic or basic environment to form the metal oxide layer. This electrochemical oxidation process is characterized by a gas-evolving reaction that results in the formation and escape of nitrogen gas from the forming metal oxide layer such that a mesoporous 3D interconnected metal oxide structure comprising a 3D network of interconnected pores is formed. This method enables the creation of metal oxide layers with specific properties suitable for various applications, including but not limited to, use in batteries, and as electrodes in molecular synthesis.

A transfer board and its forming method, packaging method, and packaging structure, the transfer board forming method comprising: providing a substrate including an interconnection region and a capacitor region, the substrate including a front side and a back side facing each other; etching the front side of the substrate to form a first groove in the substrate in the interconnection region and a second groove in the substrate in the capacitor region; forming a capacitor in the second groove; etching a portion of the thickness of the substrate below the first groove to form a conductive through-hole; forming a through-hole interconnection structure in the conductive through-hole; and thinning the back side of the substrate to expose the through-hole interconnection structure. The embodiment of the present invention also forms a capacitor in the transfer board, thereby integrating the processes of forming the capacitor and forming the transfer board, eliminating the additional step of forming the capacitor, which is beneficial for saving process steps, improving process integration, and thus reducing process costs and shortening production cycles. It also increases the functional diversity of the transfer board, thereby diversifying the application scenarios of the transfer board.

In one embodiment, a device includes (i) a first device portion including: a die substrate; at least one first dielectric layer; a first plurality of interconnects; a first encapsulation layer; and a first plurality of via interconnects located at least in the first encapsulation layer; (ii) a second device portion comprising: at least one second dielectric layer; a second plurality of interconnects; a second encapsulation layer; and a second plurality of via interconnects at least in the second encapsulation layer; and (iii) a first plurality of solder interconnects coupled to the first device portion and the second device portion, where the first plurality of interconnects, the first plurality of via interconnects, the first plurality of solder interconnects, the second plurality of interconnects, and the second plurality of via interconnects are configured to operate as inductors.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a metal level on top of a supporting structure and the metal level includes a first metal line of a first type and a second metal line of a second type, where the metal line of the first type has a first section and a second section on top of the first section, the first section includes a first type of ruthenium having a first impurity level and the second section includes a second type of ruthenium having a second impurity level, the first impurity level is lower than the second impurity level, and where the second metal line of the second type includes the first type of ruthenium and is devoid of the second type of ruthenium. A method of forming the same is also provided.

The invention provides a TGV glass substrate and a limiting growth process thereof. The limited growth process comprises the following steps: providing a glass substrate, wherein the glass substrate is provided with a front surface and a back surface which are opposite to each other; a plurality of glass through holes are formed in the glass substrate; pressing a metal foil on the back surface of the glass substrate to form a limiting substrate of the glass through hole, then growing a metal column in the glass through hole in a limiting manner, and forming a metal layer on the front surface of the glass substrate. The metal foil is introduced as the back conductive layer of the glass substrate, and a deposition process of a TGV through hole PVD seed layer is abandoned, so that economy and efficiency are improved, single-sided filling of the glass through hole is realized, a subsequent electroplating process is simplified from double-sided electroplating to single-sided electroplating, technological parameter variables are reduced by the conversion, and the production cost is reduced. The production stability and yield are improved, the thickness uniformity of the electroplated metal layer is finally improved, and a strong guarantee is provided for obtaining a high-performance and high-reliability glass through hole interconnection structure.

The invention provides a detection method for an interconnection structure, and the method comprises the steps: providing a semiconductor substrate with a to-be-detected interconnection structure, and the interconnection structure comprises an interconnection layer and a through hole interconnection structure electrically connected below the interconnection layer; a grinding process is executed to sequentially remove the interconnection layer and the through hole interconnection structure of the lower part of the interconnection layer so as to expose the surface of the residual through hole interconnection structure; performing a heat treatment on the via interconnect structure to recrystallize and shrink it; electron beam defect scanning is carried out on the shrunk through hole interconnection structure to obtain a contrast image, if a dark voltage contrast image in the contrast image can be obtained, it is judged that the electrical property of the through hole interconnection structure corresponding to the dark voltage contrast image is abnormal, and if the dark voltage contrast image in the contrast image is not obtained, it is judged that the electrical property of the through hole interconnection structure is normal. According to the invention, the detection rate and the detection accuracy of the electrical abnormality of the through hole interconnection structure can be improved.

The invention discloses a manufacturing method of a super high-rise arbitrary interconnection high-speed board. The manufacturing method comprises the following steps: manufacturing a first sub-board, a second sub-board and a third sub-board; the first daughter board, the second daughter board and the third daughter board are mutually connected through conductive copper paste; and manufacturing the outer layer. Three eight-layer daughter boards are manufactured, different layers of the daughter boards are interconnected in advance, different daughter boards are further interconnected through copper paste, and therefore the effect of any interconnection board of the super high-rise building is obtained. According to the method, the HDI plate which is high in thickness-diameter ratio and interconnected with the crossed blind holes and can be realized by 11 times of lamination in a conventional process is completed in a four-time lamination mode, the lamination times are greatly reduced, the process complexity is reduced, the production efficiency is improved, and the product quality is ensured.

The invention provides a super through hole interconnection structure and a manufacturing method thereof, and particularly relates to the field of semiconductors. The manufacturing method comprises the following steps: forming a first metal interconnection structure in a first dielectric layer; sequentially forming a second dielectric layer and a dielectric barrier layer on the first dielectric layer, wherein the etching rate of the dielectric barrier layer is smaller than that of the second dielectric layer; forming a second metal interconnection structure in the dielectric barrier layer and the second dielectric layer, wherein the top of the second metal interconnection structure is lower than the top of the dielectric barrier layer; forming a third dielectric layer on the dielectric barrier layer; a third metal interconnection structure is formed in the third dielectric layer, meanwhile, a super through hole penetrating through the dielectric barrier layer and the second dielectric layer is formed, and the third metal interconnection structure is electrically connected with the first metal interconnection structure through the super through hole. According to the manufacturing method, the problems of offset and dislocation in the etching process of the super through hole can be solved, and therefore the problems of bridging and TDDB failure are effectively solved.

A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

This invention relates to the field of bioceramic materials technology, specifically to a porous interconnected zirconia bone repair scaffold material and its preparation method. This invention aims to address the problems of poor mechanical properties and fragile interconnected structures in existing scaffolds under high porosity. The core preparation process includes: using a dual-size microsphere template, pre-fusion via acetone vapor annealing to form a stable interconnected window prototype; subsequently, constructing a continuous pore wall body by vacuum impregnation with high-viscosity zirconia slurry; then, using low-viscosity nano-zirconia sol for secondary positioning and reinforcement of the interconnected necks; finally, introducing diluted bioactive glass sol to impart surface bioactivity, followed by temperature-controlled degreasing and sintering to obtain the final product. This method, through template pre-fusion and a zoned sequential process, synergistically optimizes the scaffold's pore connectivity, mechanical strength, and bioactivity, making it suitable for the repair of weight-bearing bone defects.

The invention discloses a TSV solid-phase hole filling interconnection method and structure, and relates to the technical field of semiconductor packaging. The TSV solid-phase hole-filling interconnection method comprises the steps of S1, silicon through hole etching and deposition, S2, copper column insertion and fixation, S3, surface treatment and interconnection construction and S4, electrical testing and process feedback, a complex electroplating production line is abandoned, the through holes are filled through plastic deformation of the solid copper columns, the inherent hole and seam problems of an electroplating method are avoided, and the TSV solid-phase hole-filling interconnection method is suitable for large-scale production. The high-purity solid copper columns are high in mechanical strength and are tightly and mechanically interlocked with the inner walls of the through holes through plastic deformation, and the anti-fatigue capacity of the interconnection structure under the thermal cycle load is improved by combining the insulating layer and the barrier layer, so that reliable vertical interconnection is obtained, thermal expansion coefficient mismatch of copper and silicon is effectively avoided, and the reliability of the interconnection structure is improved. Stress is generated on the interface in the electroplating process and the subsequent thermal cycle.

The invention discloses a heat reservoir for an aerosol supply system, a heating assembly and the aerosol supply system. Wherein the heat reservoir comprises a heat storage material with a porous structure, and pores of the porous structure are interconnected to form an air channel; the heat storage material comprises stacked particles, and gaps defined by the adjacent particles define holes. Or the heat storage material comprises a three-dimensional cavernous body, and holes are defined in the three-dimensional cavernous body. Compared with the prior art, the invention provides a novel heat storage device design, namely, the heat storage device is formed by the stacked particles or the three-dimensional cavernous bodies. Furthermore, the stacked particles or three-dimensional sponge bodies are convenient to form diversified air channels, so that different air channels can be designed to meet the requirements of different products. When a zigzag and multidirectional air channel is formed by using the heat exchanger, the turbulent flow state of airflow in the air channel can be realized, and the flowing path and direction of the airflow in the channel are increased, so that the heat exchange efficiency and the heating uniformity are improved, and the heat obtained by the airflow is increased.

Systems, methods, and devices disclosed herein include three-dimensional bioprinting technologies which produce cell scaffolds with a high degree of complexity and precision. A bioprinting ink mixture can be formed with coated gold nanoparticles in an alginate-gelatin solution. Upon bioprinting a 3D scaffold microstructure from the bioink mixture, an imaging procedure is performed on the 3D scaffold microstructure using the coated gold nanoparticles as a contrasting agent. A microstructure characterization is determined from the imaging procedure, and a virtual 3D reconstruction of the microstructure characterization can be generated for presentation on a graphical user interface (GUI) of a computing device. These techniques can be used to determine whether the resultant internal core of the microstructure properly mimics the architecture of the native tissue extracellular matrix (ECM) present in-vivo by determining the degree of pore interconnectivity which can improve cell distribution, attachment, and growth in the 3D scaffold microstructure.

A device comprising a lid layer; an acoustic layer coupled to the lid layer, wherein the acoustic layer comprises: a piezoelectric layer; a dielectric layer; at least one material layer located in the dielectric layer; and a plurality of interconnects coupled to the piezoelectric layer; a cavity located between the lid layer and the piezoelectric layer; a substrate coupled to the dielectric layer of the acoustic layer; and at least one via interconnect coupled to the piezoelectric layer through the plurality of interconnects, wherein the at least one via interconnect extends through the dielectric layer and the substrate.

The invention discloses a preparation method of a silicon through hole interconnection structure, and the preparation method of the silicon through hole interconnection structure comprises the steps: providing a silicon wafer which is provided with a through hole, and the through hole is filled with conductive metal; temporarily bonding the upper surface of the silicon wafer and the upper slide; thinning one side, far away from the upper slide glass, of the silicon wafer based on a first thinning mode so as to enable the thinned silicon wafer to reach a preset thickness; the side, away from the upper slide, of the silicon wafer reaching the preset thickness is thinned on the basis of a second thinning mode, so that the thinned silicon wafer reaches the target thickness, and the thinning speed of the first thinning mode is larger than that of the second thinning mode; and performing temporary bonding on the surface, far away from the upper slide glass, of the silicon wafer reaching the target thickness and the lower slide glass, and performing de-bonding on the thinned silicon wafer and the upper slide glass to obtain the through silicon via interconnection structure. According to the method, a thin silicon wafer can be obtained, so that a vertical heat dissipation path is shortened.

A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a plurality of interconnects. The plurality of interconnects comprises a first via interconnect comprising a partial concentric planar cross section; and a second via interconnect comprising a partial ring planar cross section, wherein the second via interconnect laterally surrounds at least part of the first via interconnect.

A package comprising an integrated device and a substrate coupled to the integrated device, wherein the substrate comprises a plurality of via interconnects, and wherein at least one via interconnect from the plurality of via interconnects comprises a planar cross sectional shape that includes a concave portion.

A package comprising a metallization portion; an integrated device coupled to the metallization portion; a substrate; a plurality of wire bonds coupled to the substrate and the metallization portion; and an encapsulation layer coupled to the metallization portion. The encapsulation layer at least partially encapsulates the integrated device, the plurality of wire bonds and the substrate. The integrated device comprises a plurality of through substrate via interconnects.

An interconnect structure is provided the includes a top electrically conductive via structure that is fully-aligned to a bottom electrically conductive line structure. The interconnect structure has a maximized contact area between the top electrically conductive via structure and the bottom electrically conductive line structure without metal fangs that are caused by over etching. The dielectric surface of the interconnect dielectric material layer that is adjacent to the top electrically conductive via structure is free of reactive ion etch (RIE) damage. Further, there is no line wiggling since the bottom electrically conductive line structure is formed by a substrative metal etch. Further, there is no via distortion since the via opening used to house the top electrically conductive via structure has a density and aspect ratio that are low enough to avoid via distortion.

Dual-damascene fully-aligned via interconnects with divot fill are provided. In one aspect, an interconnect structure includes: a first interlayer dielectric disposed on a wafer; a metal line(s) embedded in the first interlayer dielectric, where a top surface of the metal line(s) is recessed below a top surface of the first interlayer dielectric; a second interlayer dielectric disposed on the first interlayer dielectric; a conductive via(s) embedded in the second interlayer dielectric and aligned with the metal line(s); a barrier layer along a bottom and a first portion of a sidewall of the metal line(s); and a protective dielectric layer along a second portion of the sidewall of the metal line(s), where the barrier layer and the protective dielectric layer fully separate the metal line(s) from the first interlayer dielectric. A metal cap can be disposed on the metal line(s). A method of fabricating an interconnect structure is also provided.

The invention discloses a single-layer porous nanosheet independent heterostructure composite film and a preparation method and application thereof, and belongs to the technical field of battery materials. The two-dimensional porous oxide and the porous graphene oxide are used as raw materials, the two materials are negatively charged and can repel each other in a solution and are stacked in a staggered manner, heterogeneous assembly is realized, the composite film with the two materials stacked alternately is formed, and a conductive frame can stably exist due to electrostatic repulsion. The porous structure and the lithium-loving characteristic of the two-dimensional porous oxide are utilized, the two-dimensional porous oxide and the porous graphene oxide form a three-dimensional porous interconnected conductive frame, a richer porous structure and more ion transmission channels are provided, the migration ability of lithium ions is effectively improved, the lithium ions can be uniformly nucleated inside, nucleation only on the surface is avoided, and the performance of the lithium ion battery is improved. And more nucleation sites are provided, the local current density is reduced, and enough space is provided for lithium storage, so that non-uniform nucleation is avoided, and the growth of lithium dendrites is inhibited.

An apparatus includes: a substrate; a first integration device coupled to the first surface of the substrate; a second integration device coupled to the first surface of the substrate; a first passive device coupled to the second surface of the substrate; and a second passive device coupled to the second surface of the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects. The plurality of interconnects includes power interconnects. The power interconnect is configured to be electrically coupled to a power source. The first integrated device, the first passive device, the second integrated device, and the second passive device are configured to be electrically coupled to the power interconnect through a first plurality of interconnects from the plurality of interconnects. The first plurality of interconnects is configured to operate as inductors, wherein the first plurality of interconnects includes via interconnects.