Silicon through hole interconnection structure and preparation method thereof

An interconnection structure and through-silicon via technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve problems such as wafer cracking

Pending Publication Date: 2020-05-19
SEMICON MFG ELECTRONICS (SHAOXING) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] Based on this, it is necessary to provide a through-silicon via interconnection structure and its preparation method for the problem of too much internal stress in the wafer caused by the cracking of the wafer during the annealing treatment or other heat treatment after the copper filling to form the TSV structure

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  • Silicon through hole interconnection structure and preparation method thereof
  • Silicon through hole interconnection structure and preparation method thereof
  • Silicon through hole interconnection structure and preparation method thereof

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Embodiment Construction

[0037] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar improvements without departing from the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0038] It should be noted that when an element is referred to as being “disposed on” another element, it may be directly on the other element or there may also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected t...

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Abstract

The invention relates to a silicon through hole interconnection structure and a preparation method thereof. The preparation method comprises the steps of: providing a substrate, and forming a siliconhole in the substrate, and forming a stress release layer and a conductive structure in the silicon hole, the stress release layer being located between the conductive structure and the substrate. According to the preparation method of the silicon through hole interconnection structure, after a barrier layer is formed, the stress release layer grows on the surface of the barrier layer. After the conductive structure is formed in the silicon hole, the conductive structure expands due to the thermal effect in the subsequent thermal process, and the stress release layer can absorb the stress generated by the expansion of the conductive structure at the moment, thereby preventing the wafer from being broken due to too much internal stress of the wafer in the annealing process or the thinning process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a through-silicon hole interconnection structure and a preparation method thereof. Background technique [0002] With the development of integrated circuit technology, integrated circuit chips have higher and higher requirements for size, speed, and power consumption, so 3D packaging technology has emerged as the times require. In the 3D packaging technology, a Through Silicon Via (TSV) structure is commonly used for interconnection. [0003] However, the number of TSV structures in existing chips is limited, so that the transfer rate of TSVs in the chip is low; this is mainly because if the number of TSVs is too large, annealing or other heat treatment after copper filling to form the TSV structure All the time will promote the growth of copper grains in the TSV structure, resulting in too much stress in the wafer, which will cause wafer cracks in the subsequent wafer th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/48
CPCH01L23/481H01L21/76898
Inventor 陈福成
Owner SEMICON MFG ELECTRONICS (SHAOXING) CORP
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