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Fast tilt correction method for QFN chip pin image

A tilt correction and image technology, applied in image analysis, image enhancement, image data processing, etc., can solve the problems of low accuracy, tilting the chip, small chip size, etc., and achieve the effect of improving the efficiency of visual inspection

Active Publication Date: 2020-04-10
JIANGSU UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There will be a certain dimensional error in the production process of QFN chips, so there will be a margin when manufacturing the loading port of the tray, but this will cause tilt when the chip is placed, which will affect the visual inspection of the chip packaging quality
[0003] At the same time, due to the small size of the chip, the manual detection and identification method with low accuracy is far from meeting the requirements of the current chip production. It is urgently needed to develop an effective technology that can quickly and accurately correct the chip image. solved problem
The research on QFN chips in the prior art mainly focuses on QFN chip structure improvement, manufacturing process, appearance inspection and QFN chip defect detection. At present, no literature and patents related to the rapid correction method of QFN chip image tilt have been found. Therefore, Designing a fast tilt correction method for QFN chip pin images to fill in the lack of existing research in this area is particularly important for improving the efficiency of visual inspection of QFN package defects

Method used

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  • Fast tilt correction method for QFN chip pin image
  • Fast tilt correction method for QFN chip pin image
  • Fast tilt correction method for QFN chip pin image

Examples

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Embodiment Construction

[0068] The following examples further illustrate the content of the present invention, but should not be construed as limiting the present invention. Without departing from the essence of the present invention, the modifications and substitutions made to the methods, steps or conditions of the present invention all belong to the scope of the present invention.

[0069] In order to improve the efficiency of visual detection of defects in QFN packaging, a fast tilt correction method for QFN chip pin image is disclosed in this embodiment, Figure 1a as the original image, with Figure 1a As the interpretation image of this embodiment, the specific correction process includes the following steps:

[0070] (1) Preprocessing the chip pin image collected by the industrial computer:

[0071] (1.1) Image filtering:

[0072] In order to remove noise and reduce image distortion, a 5×5 Gaussian filter is used to convolve with the image (such as Figure 1b ), to smooth the image and redu...

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Abstract

The invention discloses a fast tilt correction method for a QFN chip pin image. The fast tilt correction method comprises the following steps: (1) collecting the QFN chip pin image, and carrying out filtering and binarizing treatment; (2) extracting the contour of a central bonding pad of the chip image by using a polygon approximation method; (3) proposing an improved Harris corner detection algorithm, and acquiring contour vertexes; (4) carrying out straight line fitting on the vertex with a farthest distance by utilizing a least square method, and taking a straight line as an angle identification direction; and (5) rapidly correcting the chip pin image and removing white edges by taking a centroid coordinate of the image as a rotation center. The correction method provides a certain theoretical basis for correcting a QFN chip more quickly and accurately, and improves the visual detection efficiency of QFN packaging defects.

Description

technical field [0001] The invention belongs to the field of image processing algorithm design, and proposes an improved Harris corner detection algorithm, combined with a polygonal approximation method, to design a method for fast tilt correction of a pin image of a QFN chip. Background technique [0002] QFN (Quad Flat No-lead Package) is a leadless package, which is square or rectangular. It uses the middle pad at the bottom of the package to conduct heat, and there are conductive pads around the periphery of the package around the middle pad for electrical connection. There will be a certain dimensional error in the production process of QFN chips, so there will be a margin when manufacturing the loading port of the tray, but this will cause tilting when the chip is placed, which will affect the visual inspection of the chip packaging quality. [0003] At the same time, due to the small size of the chip, the manual detection and identification method with low accuracy is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06T7/00G06T7/13G06K9/32G06K9/40G06K9/46
CPCG06T7/0004G06T7/13G06T2207/10004G06T2207/20164G06T2207/30164G06V10/242G06V10/30G06V10/44
Inventor 巢渊周伟刘文汇唐寒冰李龑李兴成
Owner JIANGSU UNIV OF TECH
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