A fast tilt correction method for qfn chip pin image

A tilt correction and image technology, which is applied in image analysis, image enhancement, image data processing, etc., can solve the problems of low accuracy, tilted chip placement, small chip size, etc., and achieve the effect of improving the efficiency of visual inspection

Active Publication Date: 2022-08-09
JIANGSU UNIV OF TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

There will be a certain dimensional error in the production process of QFN chips, so there will be a margin when manufacturing the loading port of the tray, but this will cause tilt when the chip is placed, which will affect the visual inspection of the chip packaging quality
[0003] At the same time, due to the small size of the chip, the manual detection and identification method with low accuracy is far from meeting the requirements of the current chip production. It is urgently needed to develop an effective technology that can quickly and accurately correct the chip image. solved problem
The research on QFN chips in the prior art mainly focuses on QFN chip structure improvement, manufacturing process, appearance inspection and QFN chip defect detection. At present, no literature and patents related to the rapid correction method of QFN chip image tilt have been found. Therefore, Designing a fast tilt correction method for QFN chip pin images to fill in the lack of existing research in this area is particularly important for improving the efficiency of visual inspection of QFN package defects

Method used

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  • A fast tilt correction method for qfn chip pin image
  • A fast tilt correction method for qfn chip pin image
  • A fast tilt correction method for qfn chip pin image

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Embodiment Construction

[0068] The following examples further illustrate the content of the present invention, but should not be construed as limiting the present invention. Modifications and substitutions made to the methods, steps or conditions of the present invention without departing from the essence of the present invention all belong to the scope of the present invention.

[0069] In order to improve the visual detection efficiency of QFN package defects, this embodiment discloses a method for fast tilt correction of a pin image of a QFN chip. Figure 1a is the original image, with Figure 1a As an explanatory image of this embodiment, the specific correction process includes the following steps:

[0070] (1) Preprocess the chip pin image collected by the industrial computer:

[0071] (1.1) Image filtering:

[0072] In order to remove noise and reduce image distortion, a 5×5 Gaussian filter is used to convolve the image (such as Figure 1b ) to smooth the image and reduce the noticeable nois...

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Abstract

The invention discloses a fast tilt correction method for a pin image of a QFN chip, comprising the following steps: (1) collecting the pin image of the QFN chip, filtering and binarizing it; (2) extracting the center pad of the chip image by using a polygon approximation method contour; (3) propose an improved Harris corner detection algorithm to obtain contour vertices; (4) use the least squares method to fit a straight line to the farthest vertex, and use the straight line as the angle to identify the direction; (5) use the image centroid coordinates For the center of rotation, quickly correct the chip pin image and remove white edges. The correction method provides a certain theoretical basis for faster and more accurate correction of QFN chips, and improves the visual inspection efficiency of QFN package defects.

Description

technical field [0001] The invention belongs to the field of image processing algorithm design, and proposes an improved Harris corner detection algorithm, combined with a polygon approximation method, to design a fast tilt correction method for QFN chip pin images. Background technique [0002] QFN (Quad Flat No-lead Package) is a leadless package, which is square or rectangular. It uses the middle pad at the bottom of the package to conduct heat, and there are conductive pads around the periphery of the package for electrical connection. There will be a certain size error in the production process of QFN chips, so there will be a margin when manufacturing the tray carrier port, but this will cause the chip to be tilted when it is put in, which will affect the visual inspection of the chip packaging quality. [0003] At the same time, due to the small size of the chip, the manual detection and identification method with low accuracy is far from meeting the requirements of c...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06T7/00G06T7/13G06V10/24G06V10/30G06V10/44
CPCG06T7/0004G06T7/13G06T2207/10004G06T2207/20164G06T2207/30164G06V10/242G06V10/30G06V10/44
Inventor 巢渊周伟刘文汇唐寒冰李龑李兴成
Owner JIANGSU UNIV OF TECH
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