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Multi-chip packaging module

A multi-chip packaging and module technology, applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problems of affecting heat dissipation, packaging chips affecting installation, and the number of stacked layers should not be too many, so as to reduce the chip area. , to ensure the effect of heat dissipation performance

Pending Publication Date: 2020-04-14
悦虎晶芯电路(苏州)股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is also feasible to package multiple chips in a 3D stack in the vertical direction, but stacking seriously affects heat dissipation, and the number of stacked layers should not be too many, otherwise the packaged chips will be very high and affect the installation and make it difficult to dissipate heat

Method used

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  • Multi-chip packaging module
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Embodiment Construction

[0025] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments. Note that the aspects described below in conjunction with the drawings and specific embodiments are only exemplary, and should not be construed as limiting the protection scope of the present invention.

[0026] Such as figure 1 As shown, the present invention discloses a multi-chip packaging module, including: a main substrate 107, a plurality of sub-substrates 101 and a plurality of chips 100, the plurality of sub-substrates 101 are arranged on the main substrate 107 in the same direction in sequence, each Each includes an inclined surface 101 a , and each inclined surface 101 a is provided with a chip 100 , the chips 100 are electrically connected to each other, and the chip 100 is electrically connected to the main substrate 107 . Different from the vertical stacking method and horizontal spreading method in the prior art, the present inve...

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Abstract

The invention provides a multi-chip packaging module. The module comprises a main substrate, a plurality of sub-substrates and a plurality of chips, the sub-substrates are sequentially arranged on themain substrate in the same direction, each sub-substrate comprises an inclined plane, each inclined plane is provided with one chip, the chips are electrically connected, and the chips are electrically connected with the main substrate. In the invention, the plurality of chips are obliquely arranged on the sub-substrates so that a chip area and a chip spacing can be reduced to a greater extent, acertain distance can be kept between the chips, and heat dissipation performance of the chips can be ensured.

Description

technical field [0001] The invention relates to chip packaging technology, in particular to a multi-chip packaging module. Background technique [0002] The miniaturization of chips is approaching the limit, and Moore's Law will no longer apply to the development trend of chips. The chips used in current electronic products are basically packaged with a single chip. It may be a development trend in the future to package multiple chips with different functions together to achieve more powerful chip modules. This can not only reduce the size, but also reduce the distance between different ICs and increase the computing speed of the chip. [0003] The chip module formed by packaging multiple chips with different functions has been studied in the industry. The current research directions include: packaging multiple chips horizontally and packaging multiple chips vertically in 3D stack packaging . In terms of packaging materials and packaging technology, it is reasonable to ch...

Claims

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Application Information

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IPC IPC(8): H01L25/18H01L23/13H01L23/367
CPCH01L25/18H01L23/13H01L23/367H01L2224/16225H01L2224/48137H01L2924/15311
Inventor 卢耀普卢振华陈斌黄治国
Owner 悦虎晶芯电路(苏州)股份有限公司