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Viterbi decoder parallel addition, comparison and selection processing method

A technology of Viterbi decoder and processing method, which is applied in the field of parallel addition, comparison and selection processing of Viterbi decoder, and can solve the problems such as the limited rate of Viterbi decoder

Active Publication Date: 2020-04-17
JISHOU UNIVERSITY
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Problems solved by technology

However, the difference between the path metric bit width and the branch metric bit width is small, and this method can only improve the speed of the Viterbi decoder to a limited extent.

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  • Viterbi decoder parallel addition, comparison and selection processing method
  • Viterbi decoder parallel addition, comparison and selection processing method
  • Viterbi decoder parallel addition, comparison and selection processing method

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Embodiment Construction

[0040] The parallel "add-comparison-select" module includes: the first path, starting from the low bit, calculates the sum of the path metric and the branch metric bit by bit, and ends with calculating the sum of the high bit of the path metric and the high bit of the branch metric; the second path, Starting from the low bit, calculate the sum of the path metric and the branch metric bit by bit, and end with the calculation of the sum of the high bit of the path metric and the high bit of the branch metric; for the third path, once the sum of the lowest bit of the first path and the lowest bit of the second path After the sum is calculated, it starts to calculate the carry from the low bit, and ends with the output of the highest bit; finally, according to the highest carry information of the third path, the updated path metrics of the first path and the second path are selected, and Output path decision information.

[0041] The first path and the second path are both "plus" ...

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Abstract

The invention relates to a Viterbi decoder parallel addition, comparison and selection processing method, which comprises the following steps of: calculating the sum of a path metric and a branch metric bit by bit from a low bit in a first path, calculating the sum of a path metric and a branch metric bit by bit from a low bit in a second path, starting comparison once the sum of the lowest bits of the path metric and the branch metric in the first path and the second path is calculated in a third path, and finally, according to the highest carry information of the third path, selecting new path metrics respectively calculated by the first path and the second path, and outputting path judgment information. Thus, the comparison operation is converted into the addition operation, and the addition operation and the comparison operation are started from the lowest bit and ended from the highest bit at the same time, so that the delay of the addition-comparison operation in addition-comparison-selection is greatly shortened, the hardware resource consumption of the addition-comparison-selection module is reduced, and the decoding rate of the Viterbi decoder is increased.

Description

technical field [0001] The invention relates to a parallel addition, comparison and selection processing method of a Viterbi decoder, which belongs to the technical field of communication channel coding and decoding. Background technique [0002] In modern communication systems, convolutional codes are widely used due to their outstanding error correction capabilities. Viterbi decoder is a lattice-based maximum likelihood decoding algorithm, and it is an optimal probability decoding algorithm. The design structure of Viterbi decoder is simple, the calculation speed is fast, the decoding efficiency is high, and the detection gain which is 2-3dB larger than that of ordinary decision feedback scheme can be obtained. [0003] figure 1 It is a structural block diagram of a Viterbi decoder, which mainly includes 3 parts: (1) Branch Metric Unit (BMU), (2) Add-Compare-Select Unit (ACSU), (3) Survivor Path Storage + Decoding Unit. [0004] The branch measurement unit (BMU) mainly ...

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Application Information

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IPC IPC(8): H03M13/41
CPCH03M13/41Y02D30/70
Inventor 张银行曾庆立杨喜吴浩
Owner JISHOU UNIVERSITY
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