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Simplified check node processing in non-binary LDPC decoder

A technology of check nodes and decoders, which is applied in the direction of error detection coding, coding, and code conversion of multiple parity bits. It can solve problems such as non-binary codes that are not suitable for high coding rates, and achieve the effect of reducing costs.

Pending Publication Date: 2020-04-17
UNIVERSITY OF SOUTHERN BRITTANY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In particular, some practical implementations of this architecture are not suitable for the decoding of non-binary codes with high coding rates

Method used

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  • Simplified check node processing in non-binary LDPC decoder
  • Simplified check node processing in non-binary LDPC decoder
  • Simplified check node processing in non-binary LDPC decoder

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Embodiment Construction

[0076] Embodiments of the invention provide apparatus, methods and computer program products for decoding a signal encoded using at least one error correction code with reduced computational complexity and reduced latency. In particular, they provide efficient pre-ordering techniques and check node processing architectures implemented in iterative decoders for decoding signals encoded with at least one non-binary error-correcting code.

[0077] Methods, devices and computer program products according to various embodiments may be implemented in several types of digital data transmission and storage devices and systems for use in several types of applications. Exemplary devices and systems include, but are not limited to, computers, diskettes, laptops, telephones, smartphones, tape recorders, base stations, drones, satellites, and the like. Exemplary applications include magnetic and optical recording, digital television and video broadcasting, digital communications, and the l...

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Abstract

Embodiments of the invention provide an Extended Min-Sum (EMS) decoder for non-binary LDPC codes comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub- check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome. The sub-block check node may be implemented using a syndrome sub-block check node architecture, a Bubble-syndrome sub-block check nodearchitecture or a Forward-Backward sub-block check node architecture.

Description

technical field [0001] The present invention relates generally to digital communications, and in particular to methods and apparatus for decoding signals encoded using error correction codes. Background technique [0002] Error-correcting codes are effective tools implemented in various transmission or storage devices and systems to provide data protection against errors that may occur during data transmission or storage. Data errors may result from noise and / or interference. Error-correcting codes protect data from such errors by adding redundant data to the original data. [0003] Systems and devices implementing error correction codes are widely used in applications such as speech and multimedia transmission, for example in wireless communications (e.g. standardized in Wi-Fi 802.11), in radio communications (e.g. in 3G, 4G / Standardized in LTE, 5G, etc.), optical communication systems, digital video broadcasting (such as DVB-C2, DVB-S2X, DVB-T2 and other standards), and...

Claims

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Application Information

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IPC IPC(8): H03M13/11
CPCH03M13/1117H03M13/1171H03M13/1575H03M13/612H03M13/658
Inventor C·马尔尚E·布蒂永
Owner UNIVERSITY OF SOUTHERN BRITTANY