Simplified check node processing in non-binary LDPC decoder
A technology of check nodes and decoders, which is applied in the direction of error detection coding, coding, and code conversion of multiple parity bits. It can solve problems such as non-binary codes that are not suitable for high coding rates, and achieve the effect of reducing costs.
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[0076] Embodiments of the invention provide apparatus, methods and computer program products for decoding a signal encoded using at least one error correction code with reduced computational complexity and reduced latency. In particular, they provide efficient pre-ordering techniques and check node processing architectures implemented in iterative decoders for decoding signals encoded with at least one non-binary error-correcting code.
[0077] Methods, devices and computer program products according to various embodiments may be implemented in several types of digital data transmission and storage devices and systems for use in several types of applications. Exemplary devices and systems include, but are not limited to, computers, diskettes, laptops, telephones, smartphones, tape recorders, base stations, drones, satellites, and the like. Exemplary applications include magnetic and optical recording, digital television and video broadcasting, digital communications, and the l...
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