High-voltage level shift circuit and method for enhancing reliability
A level shift circuit, a technology of level shift, applied in the direction of logic circuit, logic circuit coupling/interface using field effect transistor, logic circuit connection/interface layout, etc. Solve the effect of wrong flip and avoid wrong flip
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Embodiment 1
[0042] Figure 4 with Figure 5 A schematic topology diagram and a timing diagram of the level shifting circuit 100 are shown in . The level shifting circuit 100 includes a latch 110 including a second inverter 112 cross-coupled with a first inverter 111 . The first inverter 111 includes a PMOS transistor PM1 whose source is connected to a high power domain power node providing a high power voltage HV_VDD. The first inverter 111 also includes an NMOS transistor NM1 whose source is connected to the ground node HV_VSS of the latch 110 and whose drain is coupled to the drain of the PMOS transistor PM1.
[0043]Similarly, the second inverter 112 includes a PMOS transistor PM2 whose source is connected to a high power domain power node providing a high power voltage HV_VDD. The second inverter 112 also includes an NMOS transistor NM2 whose source is connected to the ground node HV_VSS of the latch 110 and whose drain is coupled to the drain of a PMOS transistor PM2.
[0044] Th...
Embodiment 2
[0063] The core part of the latch in this embodiment is the same as that in Embodiment 1, and will not be repeated here. In order to force the latch on the high-voltage side to be in the correct state and avoid interference on the rising and falling edges of HV_VSS, Embodiment 2 provides another implementation method, that is, regardless of the ON level, the latch is on the rising and falling edges of HV_VSS Can keep the original state.
[0064] combine Image 6 As shown, the level shift circuit 200 includes coupling circuits 211 and 212 .
[0065] The coupling circuit 211 includes a capacitor C1 and a resistor R1, and the capacitor C1 and the resistor R1 are connected in series between HV_VDD and ground. There are also 4 MOS transistors between HV_VDD and HV_VSS, including PM5, PM7, NM7 and NM10, where the source of PM5 is connected to HV_VDD, the drain of PM5 is connected to the source of PM7, and the drain of PM7 is connected to NM7. Drain, the source of NM7 is connected...
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