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Apparatus and method for refreshing memory

A technology of equipment and storage body, which is applied in the direction of static memory, digital memory information, information storage, etc.

Pending Publication Date: 2020-04-21
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, conventional static row hammer refresh rate control cannot prevent bit errors due to row hammer effects that may occur at various timings for various reasons and dynamic row hammer refresh rate control may be desired

Method used

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  • Apparatus and method for refreshing memory
  • Apparatus and method for refreshing memory
  • Apparatus and method for refreshing memory

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Embodiment Construction

[0020] Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show by way of illustration certain aspects and embodiments of the invention in which it may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0021] figure 1 is a block diagram of a semiconductor device 10 including a time-based sampling circuit 11 according to an embodiment of the present invention. The semiconductor device 10 may be, for example...

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Abstract

Apparatuses for executing row hammer refresh are described. An example apparatus includes: memory banks, each memory bank of the memory banks includes a latch that stores a row address; and a time based sampling circuit. The time based sampling circuit includes: a sampling timing generator that provides a timing signal of sampling a row address; and bank sampling circuits, wherein each bank sampling circuit of the bank sampling circuits is included in a corresponding memory bank of the memory banks and provides a sampling signal to the latch in the corresponding memory bank responsive to the timing signal of sampling the row address; and an interval measurement circuit that receives an oscillation signal, measures an interval of a row hammer refresh execution based on a cycle of the oscillation signal, and further provides a steal rate timing signal for adjusting a steal rate to the sampling timing generator.

Description

Background technique [0001] High data reliability, high memory access speed, and reduced chip size are required features of semiconductor memories. [0002] A dynamic random access memory (DRAM), which is a typical semiconductor memory device, stores information by electric charges accumulated in cell capacitors, and thus information is lost unless a refresh operation is performed periodically. Therefore, a refresh command instructing a refresh operation is periodically issued from the control means, which controls the DRAM. A refresh command is issued from the control device at a frequency that all word lines must be refreshed once within one refresh cycle period (for example, 64 milliseconds). In addition, the refresh command is periodically invoked as row hammer refresh (Rhr), which maintains data retention of the victim's row address caused by the row hammer attack. [0003] However, conventional static row hammer refresh rate control cannot prevent bit errors due to row...

Claims

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Application Information

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IPC IPC(8): G11C11/406G11C11/408G11C11/4091G11C11/4076
CPCG11C11/40615G11C2211/4065G11C11/40622G11C7/22G11C11/4087G11C11/4076G11C7/1078G11C7/1051
Inventor 伊藤豊何源
Owner MICRON TECH INC
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