Clock duty ratio calibration circuit and calibration method
A technology for calibrating circuits and calibration methods, which is applied in information storage, static memory, digital memory information, etc., and can solve problems such as the inability to ensure the correctness of DRAM read data and the inability to adjust the duty cycle of clock signals
Pending Publication Date: 2020-05-22
CHANGXIN MEMORY TECH INC
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- Application Information
AI Technical Summary
Problems solved by technology
However, the existing clock calibration circuit cannot quickly and accurately adjust the duty cycle of the clock signal, so it cannot guarantee the correctness of the data read by the entire DRAM.
Method used
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[0056] In the following, only some exemplary embodiments are briefly described. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature and not restrictive.
[0057] In the first aspect, the embodiment of the present invention provides a clock duty cycle calibration circuit, such as figure 1 shown, including:
[0058] The transmission circuit 100 is used for receiving an input clock signal and sending an output clock signal. The transmission circuit 100 has at least one set of first nodes 101 and second nodes 102 .
[0059] The first pull-down circuit 200 is connected between the first node 101 and the ground 300 for discharging the first node 101 .
[0060] The second pull-down circuit 400 is connected between the second node 102 and the ground 300 for dischar...
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The embodiment of the invention provides a clock duty ratio calibration circuit and a calibration method, and the circuit comprises: a transmission circuit which is used for receiving an input clock signal and transmitting an output clock signal, and is provided with a first node and a second node; the first pull-down circuit that is connected with the first node and discharges to the first node;the second pull-down circuit that is connected with the second node and discharges to the second node; the first pull-down current regulating circuit that is connected with the first pull-down circuitand is used for changing the discharge rate of the first pull-down circuit to the first node by changing the pull-down current of the first node so as to regulate the duty ratio of the output clock signal; and the second pull-down current regulating circuit that is connected with the second pull-down circuit and is used for changing the discharge rate of the second pull-down circuit to the secondnode by changing the pull-down current of the second node so as to regulate the duty ratio of the output clock signal. According to the embodiment of the invention, the duty ratio of the output clocksignal can be quickly and accurately adjusted to about 50% by discharging different nodes on the transmission circuit.
Description
technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a clock duty ratio calibration circuit and a calibration method. Background technique [0002] This section is intended to provide a background or context to embodiments of the invention that are recited in the claims. The descriptions herein are not admitted to be prior art by inclusion in this section. [0003] In the field of DRAM (Dynamic Random Access Memory, dynamic random access memory), DDR (Double Data Rate SDRAM, double-rate synchronous dynamic random access memory) technology triggers reading data on the upper and lower edges of the clock, so a good duty cycle Clocks are also more important in the DRAM world. However, the existing clock calibration circuit cannot quickly and accurately adjust the duty cycle of the clock signal, thus failing to ensure the correctness of the data read from the entire DRAM. Contents of the invention [0004] Embodimen...
Claims
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Login to View More IPC IPC(8): G11C7/22G11C11/4076
CPCG11C7/22G11C11/4076
Inventor 不公告发明人
Owner CHANGXIN MEMORY TECH INC