Clock generation circuit and test machine

Abstract

The invention provides a clock generation circuit and a test machine, and the circuit comprises a low-frequency clock signal input module, a clock signal conversion module and a high-frequency clock signal output module; the low-frequency clock signal input module is used for accessing a low-frequency clock signal generated by the test machine; the clock signal conversion module is used for converting the low-frequency clock signal into a preset high-frequency clock signal; and the high-frequency clock signal output module is used for providing the preset high-frequency clock signal to a waferto be tested, so that the test machine can test the wafer to be tested. According to the invention, the clock signal conforming to the wafer to be tested is provided as required, and the chip test requirement is met.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a clock generating circuit and a testing machine. Background technique [0002] After the chip is produced, it is necessary to use a testing machine to test the working electrical performance of the chip to check whether the chip can work normally and meet the design requirements, so as to improve the quality of chip production. [0003] In the related art, a testing machine is usually used for testing, and usually the testing machine is directly in contact with the test board through pogo pins to directly supply a clock signal. The clock supply sub-module is designed inside the test machine. Once the test machine is developed, the type of clock provided by the test is completely determined. It cannot reach the clock test frequency in high-speed applications. It is difficult to add additional clock supply sub-modules unless a new test machine is developed. , but this solu...

AI Technical Summary

Problems solved by technology

The clock supply sub-module is designed inside the test machine. Once the test machine is developed, the type of clock provided by the test is completely determined. It cannot reach the clock test frequency in high-speed applications. It is difficult to add additional clock supply sub-modules unless a new test machine is developed. , but the cost of this scheme is very high and it is difficult to implement

However, in many high-speed applications, the requirements for the clock are relatively strict, and the clock jitter is required to be at the femtosecond level. It is difficult for general testers to meet the test requirements.

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