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Instruction disassembling method, processor, instruction disassembling device and storage medium

A technology for dismantling instructions and storing devices, which is applied in the direction of machine execution devices, electrical digital data processing, instruments, etc., and can solve problems such as different data bits, different memory access bandwidths, and unsatisfactory

Active Publication Date: 2020-06-09
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Different processors can accommodate different memory access bandwidths, and can process different data bits, which cannot meet the operation when the processed data bit width is large.

Method used

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  • Instruction disassembling method, processor, instruction disassembling device and storage medium
  • Instruction disassembling method, processor, instruction disassembling device and storage medium
  • Instruction disassembling method, processor, instruction disassembling device and storage medium

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Embodiment Construction

[0100] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0101] The terms "first", "second" and "third" in the description and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps o...

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Abstract

The invention relates to an instruction disassembling method, a processor, an instruction disassembling device and a storage medium. The instruction disassembling method comprises: according to the analyzed data size of the first source operand and a preset splitting granularity, calculating to obtain a target cycle index and a data reading capacity; reading first sub-data from a first storage device, storing currently read first sub-data into a second storage device, and executing an operation according to an operation instruction; and storing the obtained current operation result into the first storage device, and continuing to determine the data reading capacity until the current cycle index is equal to the initial value or the current cycle index is equal to the target cycle index, thereby finishing the operation corresponding to the operation instruction. By splitting and circularly reading the first source operand, splitting big data into small data for circular operation processing, and circularly reading the operand according to the data reading capacity, the size of data capable of being accommodated during operation processing meets the requirement, and the operation speed is increased.

Description

technical field [0001] The present application relates to the technical field of multi-thread scheduling, and in particular to an instruction disassembly method, a processor, an instruction disassembly device, and a storage medium. Background technique [0002] An atomic operation refers to an operation that will not be interrupted by the thread scheduling mechanism. Once this operation starts, it will run until the end without any thread switching in the middle (for example, the shared variable i performs accumulation, and multiple cores in the case of non-atomic operations At the same time, the result of i++ will be wrong). [0003] Now when a complete atomic operation instruction is executed, the complete data is processed until all the data is processed. Different processors can accommodate different memory access bandwidths, and can process different data bits, which cannot meet the operation when the processed data bit width is large. Contents of the invention [0...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/30007Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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