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A Fault Injection Method Based on Boundary Scan Test Link

A boundary scan test and boundary scan technology, applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., can solve the problems of complex fault injection methods, high hardware costs, and complicated timing, so as to facilitate the verification of test capabilities and facilitate fault injection Simple, fault-testable effects

Active Publication Date: 2021-02-02
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The fault injection methods of the above two boundary scan theories are more complicated, the hardware cost is high, software and hardware instructions are involved, and the timing is complicated

Method used

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  • A Fault Injection Method Based on Boundary Scan Test Link
  • A Fault Injection Method Based on Boundary Scan Test Link
  • A Fault Injection Method Based on Boundary Scan Test Link

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Experimental program
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Embodiment

[0035] For the convenience of description, the relevant technical terms appearing in the specific implementation are explained first:

[0036] JTAG (Joint Test Action Group): Joint Test Working Group, an international standard test protocol for boundary scan, mainly used for chip internal testing;

[0037] Port: The Boundary Scan Description Language file is used to describe all the pin information of the chip, that is, the pin name and pin attributes;

[0038] Constant: The boundary scan description language file is used to describe the mapping between different pin names and corresponding pin numbers;

[0039] TDI: Serial test instruction and serial test data input port conforming to the boundary scan test standard;

[0040] TDO: A serial test instruction and test data output port that conforms to the boundary scan test standard;

[0041] BS (Boundary Scan): boundary scan device;

[0042] Firstly, the typical format of the netlist file is introduced. Taking the Protel V1 ...

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Abstract

The invention discloses a fault injection method based on a boundary scan test link, which extracts netlist file information and boundary scan description language file information of a circuit to be tested, and then according to the netlist file information and Port information in the boundary scan description language file , Constant information to generate a boundary scan test link, modify the network where the input and output pins of the boundary scan device on the boundary scan test link are located, and generate a netlist file according to the modified network to realize short-circuit fault injection.

Description

technical field [0001] The invention belongs to the technical field of fault injection, and more specifically relates to a fault injection method based on a boundary scan test link. Background technique [0002] Boundary scan theory proposes a complete and standard test design method for large-scale integrated circuits, which overcomes the technical barriers of traditional methods when testing digital circuit boards, and uses boundary scan technology to achieve chip-level, circuit board-level, and system-level testing. Different levels of testing are of great significance for improving the testability and maintainability of digital systems. [0003] The traditional fault injection method based on the boundary scan theory often needs to combine the boundary scan protocol conversion controller to send and receive instructions or data. For example, a fault injection method is to insert instructions into the CPU instruction stream through the boundary scan link, and the CPU retu...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318533
Inventor 刘震程杰王原杨成林周秀云
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA