Low-cost circuit state control method for fault injection attack hardware simulation

Abstract

The invention discloses a low-cost circuit state control method for fault injection attack hardware simulation. The low-cost circuit state control method is used for partially scanning fault injectionattack simulation, and mainly comprises the steps: firstly, a netlist of a to-be-detected circuit is converted into an S graph, and scan flip-flops (SFFs) are selected through a balance structure; secondly, a flip-flop association graph is extracted through the S graph, the flip-flops are grouped, and in the groups, the flip-flop association graph is divided into subgraphs; and finally, the logicof the subgraphs is subjected to satisfiability detecting to guarantee that nodes of the subgraphs are controllable at the same time, and if the logic is not satisfied, parameters are modified for regrouping. The operating object of the method is the synthesized netlist, an original HDL code does not need to be modified, universality is high, and the logic expense of fault injection attack hardware simulation is remarkably reduced at the cost of additionally forming a small number of ports.

Description

technical field [0001] The invention belongs to the field of computer-aided design, in particular to a low-cost circuit state control method for fault injection attack hardware simulation. Background technique [0002] Fault injection attacks have become an effective way to attack chips [1] . In the design stage, it is necessary to evaluate the anti-fault injection attack capability of integrated circuits. literature [2] The proposed FPGA-based hardware simulation platform is cheaper than chip testing, faster than software simulation, and has the advantages of accurate fault injection. However, it is necessary to modify all D flip-flops of the circuit under test to scan flip-flops, which will Large resource consumption. Partial scanning can effectively reduce resource consumption [3-5] . Simulated fault injection attacks require injecting faults at specified times and locations while maintaining the normal state of the rest of the circuit. Partial Scan Test Method [3...

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Problems solved by technology

Therefore, the existing partial scan testing method cannot be directly applied to fault injection simulation

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