A circuit for controlling bias current

Abstract

The present invention is a circuit for controlling bias current, the circuit comprising: a reference bias current module, a mirror image module and a comparison shunt output module, the reference bias current module is connected to the mirror image module and the comparison shunt output module respectively connected to generate a reference bias current, the mirror module is respectively connected to the reference bias current module and the comparison shunt output module, and is used to mirror the reference bias current to generate the first mirror current and For a fixed bias current, the comparison shunt output module is respectively connected to the reference bias current module and the mirror module, and is used to generate a clock mirror current based on the first mirror current and the fixed bias current. The circuit provided by the invention reduces the bias current when the power supply voltage of the nonvolatile memory increases, reduces the current capability of the charge pump, and reduces the peak current on the power supply voltage when VOUT is established.

Description

technical field [0001] The invention relates to the field of nonvolatile memory, in particular to a circuit for controlling bias current. Background technique [0002] At present, the charge pump system in the non-volatile memory basically provides the non-volatile memory with the working voltage that meets the working requirements. The charge pump system includes a bias circuit, a clock circuit and a charge pump body. The current is mirrored to the clock circuit, and the clock circuit generates a clock signal to the main body of the charge pump, and the charge pump outputs a voltage according to the clock signal. [0003] The bias circuit in the charge pump system of the existing non-volatile memory is as shown in the accompanying drawings of the specification figure 1 , its working principle is: when the charge pump system is not working, according to the principle of MOS transistors, the power supply voltage VCC makes the first PMOS transistor 10 conduct, the reference v...

AI Technical Summary

Problems solved by technology

[0004] The current drive capability of the existing charge pump increases with the increase of the power supply voltage. When the settling time of the charge pump output voltage meets the requirements at the lower power supply voltage VCC, the establishment is too fast at the higher power supply voltage VCC, and due to the bias The current is basically unchanged, so that the frequency of the clock signal generated by the clock circuit is basically unchanged. The charge pump system needs to get more current from the power supply voltage VCC to ensure the current driving capability of the charge pump, resulting in a high peak current of VCC. , the higher peak current will affect the service life of the charge pump system, and also affect the performance of other circuits in the system, and the power supply noise will be relatively large, refer to figure 2 , shows the peak current of the charge pump system under different power supply voltages in the prior art, where VCC refers to the power supply voltage, IVCC refers to the peak current on VCC, and when VCC=1.5V, IVCC is about 17.5 mA , when VCC=2.0V, IVCC is about 27 mA, and when VCC=2.4V, IVCC is about 34 mA. It can be seen that with the increase of VCC, the current of IVCC increases rapidly

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