AHB bus clock domain crossing system and working method

Abstract

The invention discloses an AHB bus clock domain crossing system. The clock domain crossing system comprises a master clock data latch module, a master clock data merging module, a master clock data storage module, a slave control logic module, a slave clock data latch module, a slave clock data merging module, a slave clock data storage module and a master control logic module. The invention further discloses a clock domain crossing working method of the AHB, and read operation and write operation of data under the master clock domain and the slave clock domain are achieved. According to the invention, clock domain crossing processing of the AHB bus is realized, the delay of the clock domain crossing process can be reduced, the occupation amount of the bandwidth of the AHB bus is reduced,the bit width of a signal needing to be synchronized is reduced, and the error probability in the synchronization process is reduced.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a system and working method for an AHB bus crossing clock domains. Background technique [0002] System on Chip (System on Chip, SoC) has become a mainstream technology in the design of large-scale digital integrated circuits. SoC chips are generally composed of multiple IP modules, such as embedded central processing unit (Central Processing Unit, CPU), digital signal processor (Digital Signal Processor, DSP), various functional modules, storage modules, external interface modules, etc. The main The module (CPU) and the slave module (other sub-modules) are connected by an on-chip bus to complete the transmission of control signals and data signals. The widely used SoC bus protocol has the Advanced Microcontroller Bus Architecture (Advanced Microcontroller) of ARM Company at present. Bus Architecture, AMBA) bus protocol, AMBA protocol includes advanced extensible bus (Advanced eXtensi...

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Problems solved by technology

However, due to the inconsistency between the input clock and the module clock, it is very easy to lead to the appearance of metastable state, which will have a great impact on the overall design

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