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Dynamic self-adaptive SRAM type FPGA system fault tolerance method based on BRAM detection

A dynamic self-adaptation and system fault-tolerant technology, which is applied in the direction of non-redundancy-based fault handling, response error generation, and architecture with a single central processing unit, can solve problems such as high availability and low execution performance, and improve efficiency , Improve availability, solve the effect of unbalanced availability and performance resources

Active Publication Date: 2020-06-26
BEIHANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] As the scale of FPGA systems continues to increase, traditional fault tolerance and mitigation methods seldom consider the situation in the actual application of FPGAs. Even when there is no fault in the system, the overhead and power consumption of traditional redundancy technologies such as TMR will continue to exist, resulting in The contradiction between high system availability and low execution performance (such as throughput)

Method used

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  • Dynamic self-adaptive SRAM type FPGA system fault tolerance method based on BRAM detection
  • Dynamic self-adaptive SRAM type FPGA system fault tolerance method based on BRAM detection
  • Dynamic self-adaptive SRAM type FPGA system fault tolerance method based on BRAM detection

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Embodiment Construction

[0035] The specific implementation method described in the present invention takes the Virtex-4 XQR4VSX55 ​​SRAM FPGA which can realize dynamic partial reconstruction launched by Xilinx as an example, which can be dynamically reconstructed.

[0036] Step 1: Choose the Virtex-4 XQR4VSX55 ​​SRAM FPGA of Xilinx Company, and divide the reconfigurable area and static area by the resources of the ISE tool on the FPGA. Configure the static area function, configure it as a partial reconfiguration controller (PRC, Partial Reconfiguration Controller), configuration interface and system internal connection line (PLB, Processor Local Bus), PLB connects all components and memory controllers to the control unit . Since the static area is configured with more critical modules, it occupies less resources and cannot be partially reconstructed. All structures in this area are protected by TMR to shield the accumulation of SEU in the static area.

[0037] Step 2: Construct adaptive resources in the ...

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Abstract

The invention relates to a dynamic self-adaptive SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) system fault tolerance method based on BRAM detection, which belongs to the field of intelligent fault tolerance systems and comprises the following steps of: 1) dividing a reconfigurable region and a static region on an SRAM type FPGA; 2) constructing a dynamic adaptive structure fusing non-redundancy to multi-redundancy for a part of dynamic reconstruction area on the FPGA; 3) designing an SEU rate detection structure based on a BRAM embedded block, carrying out faultcounting, and detecting and correcting errors; 5) calculating a current turnover rate, and judging a redundancy scheme needing to be adopted; 6) implementing a redundancy scheme through a control unit of the FPGA system; and 7) calculating and evaluating the availability and performance of the adaptive FPGA system. Conditions in actual application of the FPGA are comprehensively considered, contradiction between availability and performance resources is balanced, an adaptive redundant structure of the FPGA system is dynamically changed according to the predicted radiation level (SEU rate), the task execution efficiency of the system is improved, the power consumption of the system without faults is reduced, and good portability is achieved.

Description

Technical field [0001] The invention relates to a dynamic adaptive and reconfigurable fault-tolerant method of an SRAM FPGA system. Mainly for the use of FPGA in the actual space environment, using the on-site dynamic reconfiguration characteristics of FPGA devices to optimize the adaptive dynamic reconfiguration of the FPGA system, which can be used in the fault-tolerant design of airborne and spaceborne critical electronic systems. It can prevent devices from malfunctioning due to single event effects, and can also be used for electronic products with indicators of ground radiation, which belongs to the field of intelligent fault-tolerant systems. Background technique [0002] Field Programmable Gate Array (FPGA, Field Programmable Gate Array) has changed the design of digital systems and has gradually become a core device in modern electronic products. The main feature of SRAM FPGA is that most of the programming methods are based on SRAM programming, which can be programmed ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/07G06F15/78
CPCG06F11/0793G06F15/7871Y02D10/00
Inventor 王香芬吴建新高成杨达明
Owner BEIHANG UNIV
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