ESD protection structure with low trigger voltage, integrated circuit and equipment

Abstract

The invention discloses an ESD protection structure with low trigger voltage, an integrated circuit and equipment. The ESD protection structure comprises a first P well region, a first N well region and a second P well region which are sequentially connected and arranged on a top silicon layer, wherein the first P+ region, the first N+ region, the second P+ region, the second N+ region, the thirdN+ region, the fourth N+ region and the fifth N+ region are arranged in sequence; the first P+ region and the first N+ region are located in the first P well region, the second P+ region and the second N+ region are located in the first N well region, the third N+ region is located at the joint of the first N well region and the second P well region, and the fourth N+ region and the fifth N+ region are located in the second P well region. The first P+ region and the first N+ region are in conduction connection with the cathode; and the second P + region and the second N+ region are in conduction connection with the anode. According to the structure, the circuit and the equipment provided by the invention are used for solving the technical problem of too slow protection response of ESD protection of an integrated circuit in the prior art. The ESD protection structure provided by the invention is quick in response.

Description

technical field [0001] The disclosure relates to the field of semiconductors, in particular to an ESD protection structure with low trigger voltage, integrated circuits and equipment. Background technique [0002] Electrostatic discharge (ESD, Electron Static Discharge) is an instantaneous process in which a large amount of static charge is poured into the integrated circuit from the outside to the inside when the pins of an integrated circuit are floating, and the whole process takes about 100ns. When the electrostatic discharge of the integrated circuit will generate hundreds or even thousands of volts of high voltage, the gate oxide layer of the input stage in the integrated circuit will be broken down. Damage to integrated circuits caused by electrostatic discharge is a well-known reliability problem. The continuous advancement of integrated circuit technology makes the feature size continue to decrease. On the one hand, it is beneficial to improve chip performance and...

AI Technical Summary

Problems solved by technology

A defect in the general SCR device structure is that the trigger voltage is too high

The trigger voltage of a simple SCR is equivalent to the reverse breakdown voltage of a PN junction formed by an N-well and a P-well, generally between a dozen volts and tens of volts. Such a high breakdown voltage cannot provide effective ESD protection for internal circuit components. , because before the SCR is turned on, the internal components have been damaged by the ESD pulse voltage

[0004] That is to say, the ESD protection of the integrated circuit in the prior art has the technical problem that the protection response is too slow

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