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Semiconductor chip, semiconductor wafer and manufacturing method thereof

A semiconductor and chip technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve the problems of curling of the edge of the seed metal layer, affecting the semiconductor chip packaging process, etc., and achieve the effect of preventing curling

Active Publication Date: 2022-03-04
DYNAX SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the existing manufacturing method, there may be a problem that the edge of the seed metal layer is curled, especially when the seed metal layer includes at least two metal material layers and forms an undercut structure (such as figure 2 shown), it is easy to produce the problem of edge curling of the seed metal layer, which affects the subsequent packaging process of the semiconductor chip

Method used

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  • Semiconductor chip, semiconductor wafer and manufacturing method thereof
  • Semiconductor chip, semiconductor wafer and manufacturing method thereof
  • Semiconductor chip, semiconductor wafer and manufacturing method thereof

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Embodiment Construction

[0045] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

[0046] Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art w...

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Abstract

The present application provides a semiconductor chip, a semiconductor wafer and a manufacturing method thereof, wherein the semiconductor chip includes a base, the base includes opposite first sides and second sides; the source of the semiconductor chip arranged on the first side; A through hole on the substrate, the location of the through hole corresponds to the position of the source, and the through hole penetrates from the second side to the first side; a seed metal layer formed based on the second side and electrically contacting the source through the through hole A back metal layer formed based on the seed metal layer, the back metal layer covering a part of the seed metal layer; a protective material layer covering at least the edge of the seed metal layer not covered by the back metal layer. The curling of the seed metal layer is prevented by wrapping and covering the protective material layer at the edge position of the seed metal layer not covered by the back metal layer.

Description

technical field [0001] The present application relates to the technical field of semiconductors, in particular, to a semiconductor chip, a semiconductor wafer and a manufacturing method thereof. Background technique [0002] Please refer to figure 1 , some transistor-like semiconductor devices usually include a source S, a drain D, a gate G, and a substrate B. In the use environment of such semiconductor devices, the source and the substrate often need to be grounded. In some implementations, in order to increase the gain of the semiconductor device and reduce the ground inductance, a through hole through the substrate is opened on the substrate, and then filled with metal to contact the source of the semiconductor device, so that the The source is connected to the backside metal layer which is grounded on the backside of the substrate to reduce the source-to-ground inductance. In this way, usually a seed metal layer extending through a through hole to electrically contact...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/58H01L29/78
CPCH01L23/58H01L29/78
Inventor 潘盼
Owner DYNAX SEMICON