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Full adder, half adder, data processing method, chip and electronic equipment

A technology of full adder and half adder, applied in the fields of full adder, data processing method, chip and electronic equipment, and half adder, can solve the problem of high power consumption of full adder and half adder

Active Publication Date: 2020-07-07
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, in the operation process, most full adders and half adders use logic gate circuits such as XOR gates for operations, resulting in high power consumption of full adders and half adders

Method used

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  • Full adder, half adder, data processing method, chip and electronic equipment
  • Full adder, half adder, data processing method, chip and electronic equipment
  • Full adder, half adder, data processing method, chip and electronic equipment

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Embodiment Construction

[0065] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0066] The full adder and half adder provided in this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for calculation and processing. The specific structure The schematic diagrams are as figure 1 and figure 2 shown.

[0067] Such as figure 1 Shown is a schematic structural diagram of a full adder provided by an embodiment. The full adder includes: a logic circuit 11, a first gating circuit 12, a second gating circuit 13 and a selection circuit 14; the output end o...

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PUM

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Abstract

The invention provides a full adder, a half adder, a data processing method, a chip and electronic equipment. The full adder comprises a logic circuit, a first gating circuit, a second gating circuitand a selection circuit; the half adder comprises a logic circuit, a gating circuit and a selection circuit; according to the full adder, part of circuits in the full adder can be selectively closed,and the power consumption of the full adder is reduced, so that the performance of the AI chip is improved; and besides, the half adder can selectively close a part of circuits in the half adder, andthe power consumption of the half adder is reduced, so that the performance of the AI chip is improved.

Description

technical field [0001] The invention relates to the technical field of computers, in particular to a full adder, a half adder, a data processing method, a chip and electronic equipment. Background technique [0002] With the rapid development of various artificial intelligence (AI) chips, the requirements for high-performance digital systems are getting higher and higher. In digital systems, full adders and half adders are integral parts of computing modules such as full adders, full adders, half adders, and comparators, and neural network algorithms are one of the algorithms widely used in smart chips. , in the neural network algorithm, full adders, half adders, full adders, comparators and other computing modules need to be used many times, therefore, the performance of the internal basic full adder and half adder is very important for AI chips Particularly important. [0003] Existing full adders and half adders are generally composed of XOR gate logic circuits, AND gat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/20G06F7/501
CPCH03K19/20G06F7/501Y02D10/00
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD