3D NAND memory and manufacturing method thereof

Abstract

The invention provides a 3D NAND memory and a manufacturing method thereof. Before a grid line gap is formed, a first part selection grid tangent line is formed at a position where a common source electrode contact part is to be formed; the width of the first top selection grid tangent line is greater than that of the grid line gap, so the formed common source contacts the periphery; the stacked layer is replaced by the insulating material for forming the top selection gate tangent, so that a forming window for forming the contact part of the common source electrode is enlarged, even if the contact part is slightly deviated from the common source electrode, the contact part cannot be in contact with the gate layers on the two sides of the bridging common source electrode, the electric leakage risk of the device is reduced, and the yield of the device is improved. Meanwhile, the forming window of the contact part is enlarged, so that the manufacturing difficulty of the contact part is reduced to a certain extent. In addition, the first top selection gate tangent line and the second top selection gate tangent line can be formed by using the same mask, so that the preparation of the mask and the etching step are saved, and the manufacturing cost of the memory is reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit are increasingly favored. [0003] In the 3D NAND process, gate line gaps are usually formed to form stacked gate layers. In order to control the effective gate area, the size of the gate line gaps needs to be limited, thus making the size of the gate line gaps very limited. When the common source is subsequently formed through the gate line gap and the contact part of the common source is further formed, the position of the contact part and the common source is slightly deviated, which will cause the contact part to bridge the gate layers on both sides of the common source...

AI Technical Summary

Problems solved by technology

[0003] In the 3D NAND process, gate line gaps are usually formed to form stacked gate layers. In order to control the effective gate area, the size of the gate line gaps needs to be limited, thus making the size of the gate line gaps very limited. When the common source is subsequently formed through the gate line gap and the contact part of the common source is further formed, the position of the contact part and the common source is slightly deviated, which will cause the contact part to bridge the gate layers on both sides of the common source, resulting in leakage and other hazards, seriously affecting the use of the device

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