44results about How to "Fewer etch steps" patented technology

The invention provides a manufacturing method for stepped silicon germanium source / drain structures, which includes firstly, providing a silicon substrate, wherein a grid structure, first gap walls on two sides of the grid structure and second gap walls on two sides of each first gap wall are formed on the silicon substrate, secondly, performing multiple times of ion implantation technology by different directions and depths to form a first amorphous state region in the silicon substrate on two sides of each second gap wall and form at least one second amorphous state region in the silicon substrate below the second gap walls, thirdly, removing the second gap walls, fourthly, removing the first amorphous state regions and the second amorphous state regions to form a stepped recess, and fifthly, forming a doped stepped silicon germanium source / drain structure in the stepped recess. Compared with the prior art, the manufacturing method for stepped silicon germanium source / drain structures can reduce etching procedures and lower control difficulty of the etching process.

The invention relates to the manufacturing field of semiconductors, in particular to a manufacturing process for a copper interconnection line. According to the manufacturing process for the copper interconnection line disclosed by the invention, silanization materials are adopted in a trench-preference copper interconnection process to form an isolating film between two layers of photoresists in a dual-exposure technology, and through holes and metal trench structures in the photoresists are transferred to dielectric layers in sequence, so that the existing process, in which the etching of the metal trench and the etching of the through hole are carried out in two independent steps, can be replaced, the etching steps in dual-Damascus metal interconnection line process are effectively reduced, the production capacity is increased and the manufacturing cost is reduced.

The invention relates to a direct-light-emitting-type micro display array device and a preparation method thereof. A display array comprises a substrate epitaxial wafer, semiconductor matrix isolating regions, electron-type conducting layers, light emitting layers, hole-type conducting layers, electron-type conducting electrodes, hole-type conducting electrodes, isolating protection layers, anode lines and cathode lines. The preparation method comprises the steps of: etching an epitaxial layer by adopting a dry-process etching method to obtain the electron-type conducting layers and form a plurality of array units; implanting ions into the electron-type conducting layers till to a substrate by adopting an ion implantation method to realize isolation of adjacent units and obtain the semiconductor matrix isolating regions; evaporating metal through electron beams to form the electron-type conducting electrodes and leading out the cathode lines; depositing the isolating protection layers through PECVD (Plasma Enhanced Chemical Vapor Deposition); and evaporating metal through electron beams to form the hole-type conducting electrodes and leading out the cathode lines, wherein regions formed by the anode lines and the cathode lines which are spatially intersected are display pixels.

The invention discloses a method of manufacturing a circuit pattern through a sputtering technology and a rewiring method of a chip; the method of manufacturing the circuit pattern through the sputtering technology comprises the following steps of: arranging a jig between a component to be sputtered and a cathode of sputtering equipment, and arranging a through groove with a set shape on the jig; starting the sputtering equipment, leading atoms sputtered by the cathode to pass through the through groove and then be adhered on the surface of the component, and forming the circuit pattern. According to the technical scheme of the embodiment, the circuit pattern with the set shape can be directly manufactured by sputtering; and compared with the traditional technical scheme of firstly sputtering a whole surface and then etching the circuit pattern, the technical scheme has the advantages that an etching step is omitted, a technological process is shortened and the technology difficulty is reduced.

The invention relates to the semiconductor manufacture field and particularly relates to a manufacture process of a copper interconnection line. According to the manufacture process of the copper interconnection line, an isolating membrane is formed between two layers of light resistance in a double exposure technology by using cross-linking materials in a copper interconnection process with grooves preferred, and through holes and metal groove structures in the light resistance are transferred to a media layer successively, so that the prior art that metal groove etching and through hole etching are divided into two independent steps is replaced, etching steps in a dual damascene metal interconnection line process are effectively reduced, the productivity is improved, and the manufacture cost is decreased.

The invention relates to the field of MOS (Metal Oxide Semiconductor) devices, particularly to a double-structure contact hole synchronous-etching technology. The silicon nitride barrier layer in a photosensitive area is removed immediately after a silicon nitride barrier layer is deposited, so that the deposit layer structure of a double-structure contact hole of a CIS (Complementary Metal Oxide Semiconductor Image Sensor) product is changed; the etching selection ratio of an interlayer dielectric layer (insulating dielectric layer) to the barrier layer and a silicone substrate is enlarged in the follow-up etching technology, so that the etching step special for a monox barrier layer at the bottom of the photosensitive area is reduced, the monox loss on STI (Shallow Trench Isolation) of a borderless contact hole in a logic area is reduced while the double-structure contact hole is formed, and the yield of products is improved while the technological reliability and stability are enhanced.

The invention discloses a through-hole-priority dual damascene copper interconnection method for reducing coupling capacitance of redundant metal. According to the through-hole-priority dual damascene copper interconnection method for reducing the coupling capacitance of the redundant metal, a dielectric layer is firstly deposited on a substrate silicon wafer and then the dielectric layer is coated with first photoresist; a through hole and a redundant metallic groove are formed in a first photoresist film through exposure and development, and the metallic groove formed in the first photoresist penetrates through the first photoresist; in the same developing machine, the first photoresist is coated with a SAFIER to solidify the through hole and the redundant metallic groove which are formed in the first photoresist, the SAFIER can react with the surface of the first photoresist to form an isolating film which can not dissolve in second photoresist under the heating condition, and then the remaining SAFIER which does not react with the surface of the first photoresist is removed; the first photoresist on which the isolating film is formed is coated with the second photoresist, and the anti-etching capacity of the first photoresist is larger than that of the second photoresist; a metallic groove located in the through hole is formed in a second photoresist film through exposure and development.