Method for converting Avalon bus into Axi4 bus

Abstract

The invention discloses a method for converting an Avalon bus into an Axi4 bus. The method comprises: when an Avalon bus is an Avalon_st bus, receiving Avalon_st bus data, carrying out logic processing on the received Avalon_st bus data and then outputting corresponding Axi4_st bus data; and when the Avalon bus is an Avalon_mm bus, receiving signals transmitted by each channel of the Avalon_mm bus, framing the signals, storing the framed signals into the asynchronous FIFO, reading the signals from the asynchronous FIFO when equipment corresponding to the Axi4 bus is ready, and outputting the signals to the corresponding channels of the Axi4 bus according to the time sequence relationship of the Axi4 bus. According to the method, the Avalon bus can be converted into the Axi4 bus in a time-delay-free and clock-domain-crossing mode, and rapid design and interface matching work are achieved in a cross-platform universal design or code transplantation scheme.

Description

technical field [0001] The present application relates to the technical field of data conversion, in particular to a method for converting an Avalon bus to an Axi4 bus; it also relates to a device, equipment and a computer-readable storage medium for converting an Avalon bus to an Axi4 bus. Background technique [0002] The Avalon bus is an internal interconnect bus technology developed by Altera, which can be automatically generated by the QSYS tool without user intervention. It is often used as an ideal inline bus between the system processor and peripherals. At the same time, the Avalon bus has independent address, data, and control lines, supports data widths within 128 bits, supports synchronous operations, and does not require complex handshaking / response mechanisms. Therefore, the Avalon bus is widely used flexibly. The Axi4 bus is a high-performance, high-bandwidth, and low-latency on-chip bus proposed by AMBA. Its main feature is that the address / control and data ar...

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Problems solved by technology

However, this IP can only be used on the Xilinx platform, which has a large delay, and does not support cross-clock domain conversion, so its use is limited

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