Convolutional network accelerator, configuration method and computer readable storage medium

Abstract

The invention belongs to the technical field of hardware acceleration of a convolutional network. The invention discloses a convolutional network accelerator, a configuration method and a computer readable storage medium. The method comprises the steps: judging the number of layers, where a whole network model is located, of a currently executed forward network layer through a mark; obtaining a configuration parameter of the currently executed forward network layer, and loading a feature map and a weight parameter from a DDR through the configuration parameter; meanwhile, the acceleration kernel of the convolution layer configures the degree of parallelism according to the obtained executed forward network layer configuration parameters. According to the method, the network layer structureis changed through configuration parameters, only one layer structure can be used when the network FPGA is deployed, flexible configurability is achieved, and meanwhile the effect of saving and fullyutilizing on-chip resources of the FPGA is achieved. A method of splicing a plurality of RAMs into an overall cache region is adopted, the bandwidth of data input and output is improved, ping-pong operation is adopted, and therefore feature map and weight parameter loading and accelerator operation are in pipeline work.

Description

technical field [0001] The invention belongs to the technical field of hardware acceleration of convolutional networks, and in particular relates to a convolutional network accelerator, a configuration method and a computer-readable storage medium. Background technique [0002] At present, with the development of deep learning technology, convolutional neural network is more and more widely used in computer vision, such as target detection and recognition, tracking, semantic segmentation, speech recognition and natural language processing. Its outstanding data fitting performance And the versatility of the model makes the application of convolutional neural network in various complex scene fields replace the original traditional modeling method and become the benchmark in this field. But at the same time, the powerful data fitting ability is at the cost of a huge amount of data and calculation. For example, the model size of AlexNet is 233MB, and the calculation amount is 0....

AI Technical Summary

Problems solved by technology

[0005] To sum up, the existing problems in the existing technology in many convolutional network hardware acceleration schemes implemented on FPGA are: (1) they are all aimed at a specific network structure model,

[0006] (2) All the network layers of the model are implemented on the chip. This method can only be used for some smaller networks, or the FPGA resources are not fully utilized.

[0007] (3) Time-sharing multiplexing is not achieved, and the degree of parallelism is low

[0008] Difficulty in solving the above technical problems: Among the public solutions for implementing convolutional neural networks on FPGA, there is no good general-purpose implementation solution, and at the same time, resource consumption needs to be considered while achieving high parallelism

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