Leakage current reduction in dual rail device

Abstract

A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level whichis lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

Description

technical field [0001] The present invention relates to power management in dual rail devices, and more particularly to devices and methods for reducing leakage current. Background technique [0002] A dual-rail processor separates the voltage of the memory cells from the voltage of the logic circuits. This separation allows memory cells to have stable voltages within safe voltage ranges, while logic circuit voltages can be reduced to reduce power consumption. The reduction in power consumption is directly related to the battery life of battery-powered devices such as mobile devices and Internet-of-things (IoT) devices. To further extend battery life, the device controls the leakage current flowing through its logic circuits when the device is not in use, such as in a sleep or standby state. The reduced leakage power during sleep states significantly extends the operating time of battery-powered devices. [0003] One approach for leakage power reduction is to shut down th...

AI Technical Summary

Problems solved by technology

However, these techniques either do not achieve sufficient power reduction or result in additional circuitry or a significant increase in system complexity

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