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Leakage current reduction in dual rail device

A leakage current and circuit technology, applied in the field of power management, can solve problems such as additional circuits or increased system complexity

Pending Publication Date: 2020-07-28
MEDIATEK SINGAPORE PTE LTD SINGAPORE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, these techniques either do not achieve sufficient power reduction or result in additional circuitry or a significant increase in system complexity

Method used

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  • Leakage current reduction in dual rail device
  • Leakage current reduction in dual rail device
  • Leakage current reduction in dual rail device

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Embodiment Construction

[0018] In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. From the included description, those skilled in the art will be able to implement the appropriate function without undue experimentation.

[0019] Embodiments of the present invention reduce leakage current for dual rail devices. The device may be a system-on-a-chip (SOC) device, which further includes a memory cell array, peripheral logic and core logic. The device may be a processing device with embedded storage. The device can be a mobile device, an IoT device, or another low power device that can...

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Abstract

A device for reducing leakage current includes a memory cell array, a power switch and a core logic. The memory cell array is electrically connected to a first power rail which supplies a first voltage level. The core logic circuitry is electrically connected to a second power rail via the power switch when the power switch is turned on. The second power rail supplies a second voltage level whichis lower than the first voltage level. The power switch is to be turned off by the first voltage level supplied to a gate terminal of the power switch, to thereby disconnect the core logic circuitry in a sleep state from the second power rail.

Description

technical field [0001] The present invention relates to power management in dual rail devices, and more particularly to devices and methods for reducing leakage current. Background technique [0002] A dual-rail processor separates the voltage of the memory cells from the voltage of the logic circuits. This separation allows memory cells to have stable voltages within safe voltage ranges, while logic circuit voltages can be reduced to reduce power consumption. The reduction in power consumption is directly related to the battery life of battery-powered devices such as mobile devices and Internet-of-things (IoT) devices. To further extend battery life, the device controls the leakage current flowing through its logic circuits when the device is not in use, such as in a sleep or standby state. The reduced leakage power during sleep states significantly extends the operating time of battery-powered devices. [0003] One approach for leakage power reduction is to shut down th...

Claims

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Application Information

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IPC IPC(8): G11C5/14
CPCG11C5/147G11C11/417G11C2207/2227G11C5/14
Inventor 森迪尔库玛尔·贾亚帕刘超群吴一品苏志强
Owner MEDIATEK SINGAPORE PTE LTD SINGAPORE