SRAM read-write structure and test method thereof

Abstract

The invention provides an SRAM read-write structure and a test method thereof. The SRAM read-write structure comprises a first PMOS, a second PMOS, a first NMOS, a second NMOS, a third NMOS and a fourth NMOS. The first PMOS and the first NMOS as well as the second PMOS and the second NMOS form two pairs of mutually crossed coupling inverters; the third NMOS is connected to the input end Q of a phase inverter, and the fourth NMOS is connected to the output end QB of the phase inverter to interact data stored in the SRAM read-write structure with a peripheral circuit; and the back gates of the third NMOS and the fourth NMOS are respectively connected with voltages VBG. According to the invention, the back gates of the third NMOS and the fourth NMOS are respectively connected out and bias voltages are applied, and the balance of electrical parameters is searched in the test process, so that the conductivity of the third NMOS is poorer than that of the first NMOS during reading operation,the conductivity of the fourth NMOS is better than that of the second PMOS during writing operation, and the coordination of the read-write capability of the device is realized.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM read-write structure and a testing method thereof. Background technique [0002] In chip design, the storage unit SRAM has been widely studied due to its fast access and stable data storage capabilities. In practical applications, parameters such as the stability and read and write capabilities of SRAM storage units are hot research issues. Traditional SRAM is divided according to the number of transistors required to form a basic unit, and can be divided into four-tube SRAM, six-tube SRAM and N-tube SRAM (N>6). Among them, the six-transistor (6T) SRAM cell has become the mainstream standard cell structure in the current industry due to its advantages such as simple structure, small area, and good data storage stability. The core part of the SRAM unit is composed of two pairs of cross-coupled inverters, which are connected end to end to form positive feedback t...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a SRAM read-write structure and its testing method, which is used to solve the problem that the conventional six SRAM units in the prior art cannot coordinate the reading stability and writing ability well. The problem

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