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Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus

A technology for information processing equipment and computing devices, which is applied in inference methods, architecture with a single central processing unit, and computing using non-contact manufacturing equipment, etc. problem, to achieve the effect of suppressing the degradation of the processing performance

Pending Publication Date: 2020-08-18
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the system cost increases and the time to provide the multimodal DNN inference system to the user increases

Method used

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  • Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus
  • Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus
  • Information processing apparatus, arithmetic processing device, and method of controlling information processing apparatus

Examples

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Embodiment Construction

[0056] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0057] figure 1 An example of the information processing device according to the embodiment is shown. figure 1 The illustrated information processing apparatus 100 includes a plurality of arithmetic devices 2 ( 2A, 2B, and 2C) and an arithmetic device 6 , and executes multimodal deep neural network (DNN) inference processing. The arithmetic means 2A, 2B, or 2C is an example of a first pre-processing arithmetic means, and the arithmetic means 6 is an example of a first post-processing arithmetic means and an arithmetic processing means.

[0058] The arithmetic device 2A includes a conversion unit 3A, an arithmetic unit 4A, and an output unit 5A. The arithmetic device 2B includes a conversion unit 3B, an arithmetic unit 4B, and an output unit 5B. The arithmetic device 2C includes a conversion unit 3C, an arithmetic unit 4C, and an output unit 5C. The conversion unit 3 ( 3A, 3B, o...

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PUM

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Abstract

The invention relates to an information processing apparatus, an arithmetic processing device, and a method of controlling the information processing apparatus. The information processing apparatus includes a first preprocessing arithmetic device configured to execute preprocessing for analog data from a first sensor; and a first post-processing arithmetic device connected to the first preprocessing arithmetic device and configured to execute post-processing for first preprocessed data output by the first preprocessing arithmetic device, wherein the first preprocessing arithmetic device includes a first conversion unit configured to receive the analog data from the first sensor and convert the analog data into digital data, a first preprocessing arithmetic unit configured to output featuredata on the basis of a result of execution of feature extraction processing for the digital data, and a first output unit configured to output the feature data, and the first post-processing arithmetic device includes a first input unit configured to input the feature data,a first storage unit configured to store the feature data, and a first post-processing arithmetic unit configured to cause the first storage unit to store recognition result data on the basis of a result of execution of recognition processing for the feature data.

Description

technical field [0001] The embodiments discussed herein relate to an information processing device, an arithmetic processing device, and a method of controlling an information processing device. Background technique [0002] In a neural network such as a deep neural network (hereinafter also referred to as DNN), each of a plurality of neurons included in each layer is connected to a plurality of neurons included in other layers, and each neuron Perform product-and operations, etc. Therefore, the calculation amount becomes huge. Therefore, in order to reduce the amount of calculation, some neurons included in the neural network are removed, or the dimension of the parameter matrix is ​​reduced (for example, see Patent Document 1 and Patent Document 2). Alternatively, in order to reduce the amount of computation, in the case where the output value of a neuron of a layer for detecting a feature is equal to or smaller than a predetermined threshold, the output value is not sto...

Claims

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Application Information

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IPC IPC(8): G06N3/04G06N3/063G06F15/17G06F15/78G06V10/764
CPCG06N3/063G06F15/17G06F15/7807G06N3/045G06N3/08G06V10/82G06V10/764G06N3/048G06N3/044G06F7/48G06N3/02G06N5/04G10L25/51G06F18/253
Inventor 高田辽日下田雅纪
Owner FUJITSU LTD
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