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Chip packaging method

A chip packaging and chip technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of high brittleness, high cost, and low stability of packaged devices in silicon interposers, so as to improve performance and reduce Packaging cost, the effect of increasing the signal transmission rate

Active Publication Date: 2020-08-18
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The packaged device formed by the above method has excellent electrical properties and thermal conductivity, but the cost is high, and the silicon interposer is highly brittle, resulting in low stability of the packaged device

Method used

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Embodiment Construction

[0033] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by a person of ordinary skill in the art without creative work shall fall within the protection scope of this application.

[0034] See figure 1 , figure 1 It is a schematic flowchart of an embodiment of the chip packaging method of the present application, and the packaging method includes:

[0035] Step S101: Provide a group of adjacently arranged first chip 22 and second chip 24.

[0036] Specifically, see figure 2 , figure 2 Yes figure 1 A schematic structural diagram of an embodiment corresponding to step S101. The first chip 22 includes a functional surface 220 and...

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Abstract

The invention discloses a chip packaging method, and the method comprises the steps of providing a group of a first chip and a second chip which are arranged adjacently, and arranging the signal transmission regions on the functional surfaces of the first chip and the second chip adjacently, wherein the heights of the signal transmission regions of the first chip and the second chip to be smallerthan the heights of non-signal transmission regions of the first chip and the second chip; electrically connecting the connecting bonding pads on the functional surface of the connecting chip with thebonding pads on the signal transmission regions of the first chip and the second chip; and enabling the functional surfaces of the first chip and the second chip and the non-functional surface of theconnecting chip to face the packaging substrate, and enabling the non-signal transmission regions of the first chip and the second chip to be electrically connected with the packaging substrate. Through the above mode, the signal transmission rate between the first chip and the second chip can be improved, and the performance of the packaging device is improved.

Description

Technical field [0001] This application relates to the field of semiconductor technology, in particular to a chip packaging method. Background technique [0002] With the upgrading of electronic products, the requirements for chip packaging technology are getting higher and higher. In the existing chip packaging technology, the chip and the silicon interposer are usually connected first, and then the silicon interposer and the substrate are connected. The packaged device formed in the above manner has excellent electrical performance and thermal conductivity, but the cost is relatively high, and the silicon interposer is relatively brittle, resulting in low stability of the packaged device. Therefore, it is necessary to develop a new packaging technology that can reduce the cost and the performance of the formed packaging device is excellent. Summary of the invention [0003] The main technical problem to be solved by this application is to provide a chip packaging method that ca...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/60
CPCH01L24/81H01L21/76895H01L2224/81986H01L2224/16225H01L2224/73204H01L2224/32225H01L2224/92125H01L2224/12105H01L2924/00
Inventor 李骏戴颖
Owner NANTONG FUJITSU MICROELECTRONICS