Method for forming CMOS on-chip three-dimensional structure

Abstract

The invention discloses a method for forming a CMOS on-chip three-dimensional structure. The method comprises the following steps of forming an annular raised monocrystalline silicon seed layer regionon a silicon substrate; forming a first-layer CMOS transistor in a non-seed layer region; forming a first interlayer dielectric layer, and exposing the monocrystalline silicon seed layer region; covering the first interlayer dielectric layer with a polycrystalline silicon layer, and enabling the surfaces of the polycrystalline silicon layer and the first interlayer dielectric layer to be flush; heating to melt and recrystallize the polycrystalline silicon layer, and converting polycrystalline silicon into monocrystalline silicon by using monocrystalline silicon surrounding the polycrystallinesilicon to form a monocrystalline silicon layer; forming a second-layer CMOS transistor on the monocrystalline silicon layer; forming a second interlayer dielectric layer; and forming interconnectionbetween the first-layer CMOS transistor and the second-layer CMOS transistor. According to the invention, the density of the on-chip CMOS transistor can be increased, the required interconnection length is reduced, the product performance is improved, and the cost of a single chip is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a method for forming a three-dimensional structure in a CMOS chip. Background technique [0002] With the development of semiconductor VLSI, the existing technology has approached the physical limit. Driven by the further miniaturization and multi-functionalization of electronic products, other new technologies, new materials, and new technologies have been explored. Removing the two-dimensional limitation of the chip and developing the chip structure to three-dimensional is one of them. At present, the method of making three-dimensional structure can be roughly divided into two types, one is to stack silicon wafers through bonding technology to realize the metal interconnection structure on the three-dimensional level; the other is to make multi-layer CMOS transistors in the chip to realize On-chip 3D structure. [0003] The existing sil...

AI Technical Summary

Problems solved by technology

The main problem is that the three-dimensional structure on the chip needs to form multiple layers of single crystal silicon to make CMOS devices

However, currently commonly used methods, such as monocrysta

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