A kind of multi-chip package and its manufacturing method

Abstract

The invention provides a multi-chip package and a manufacturing method thereof. The multi-chip package of the present invention utilizes the through hole formed on the inclined side to be electrically connected to the active area of ​​the chip, which can realize the electrical connection of the short path to the substrate substrate, and can realize miniaturized packaging and save lateral space; and each chip The other side of the chip can realize flexible interconnection between chips, ensuring the flexibility and high integration of multi-chip packaging.

Description

Technical field [0001] The present invention relates to the field of semiconductor chip packaging, specifically to a multi-chip packaging and manufacturing method thereof. Background [0002] For semiconductor packaging, multi-chip packaging can achieve miniaturization, multi-functionality and low cost, but with the continuous improvement of requirements, the thinness and multi-function of multi-chip packaging need to be further improved, how to achieve a smaller package on the basis of existing silicon chips, is the goal of the field has been pursuing. US2011 / 079890A1 discloses a semiconductor package, which will be a plurality of bare cores staggered on each other stacked sequentially on the substrate substrate, the arrangement saves a part of the space laterally, but its staggered arrangement first brings instability of the electrical connection, and its horizontal still needs to occupy a large space, is not conducive to the realization of miniaturized package CN104332462A dis...

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Problems solved by technology

US2011 / 079890A1 discloses a semiconductor package, in which a plurality of bare cores are stacked on the base substrate sequentially in a staggered manner. This arrangement saves a part of the space in the lateral direction, but the staggered arrangement first brings about the need for electrical connection. Instability, and it still needs to occupy a large space in the lateral direction, which is not conducive to the realization of miniaturized packaging. CN104332462A discloses a wafer-level packaging unit in which chips are stacked obliquely, which places multiple chips obliquely on the substrate. And using the pads close to the substrate for direct electrical connection, the electrical connection path is relatively short, but its lateral space utilization and the stability of the package are poor

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