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Three-dimensional multi-chip parallel packaging structure

A multi-chip, parallel technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problem of increasing the installation area of ​​semiconductor devices, and achieve the effect of reducing the installation area

Pending Publication Date: 2020-10-09
YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Increases the installation footprint of semiconductor devices in products, and there are many limitations in practical applications

Method used

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  • Three-dimensional multi-chip parallel packaging structure
  • Three-dimensional multi-chip parallel packaging structure
  • Three-dimensional multi-chip parallel packaging structure

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Embodiment Construction

[0017] Combine the following Figure 1-3 Further explain the present invention, including frame 1, chip 2 and jumper wire 3, the frame includes frame A11 and frame B12, and chip layer 1, chip layer 2 ... chip layer n, n are stacked on the frame B12 from bottom to top in sequence ≥2; the polarities of the opposite faces of adjacent chip layers are the same,

[0018] A jumper wire Ak connecting the frame A is provided on the top surface of the odd-numbered layer of the chip layer, and k is 1, 3, 5...n;

[0019] A jumper Bj connecting the frame B is provided on the top surface of the even-numbered layer of the chip layer; j is 2, 4, 6...n;

[0020] The sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layer. n is a numerical serial number.

[0021] Each chip layer is stacked with m chip monomers according to the form of serial connection, m≥1. m is the quantity number.

[0022] The tin layer 4 used for connection between the frame 1, the ...

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Abstract

The invention discloses a three-dimensional multi-chip parallel structure. The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device with a multi-diode chip parallel structure. The three-dimensional multi-chip parallel structure provided by the invention increases the overcurrent capacity of a device without increasing the area occupied by installation of the device. The structure comprises a frame, chips and jumper wires. The structure is characterized in that the frame comprises a frame A and a frame B; a chip layer 1, a chip layer 2, ...,a chip layer n are sequentially stacked on the frame B from bottom to top, and n is greater than or equal to 2; the polarities of the opposite faces of the adjacent chip layers are consistent; the sum of the jumper wires Ak and the jumper wires Bj is consistent with the number of the chip layers; and n is a number sequence number. According to the invention, plane spreading of multiple chips is changed into three-dimensional stacking, and series packaging of the multiple chips is changed into parallel packaging of the multiple chips, so an area occupied by installation of the packaging body is reduced. In addition, the three-dimensional multi-chip parallel structure can formulate different over-current capabilities and voltage withstanding capabilities, thereby meeting the use requirements of different application scenes.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a semiconductor device with a parallel structure of multiple diode chips. Background technique [0002] With the development of the electronic information industry, products tend to be miniaturized and miniaturized, which has certain requirements for the size of semiconductor device packages. Traditional multi-chip packaging can only spread chips on a plane, and then connect them in series through jumpers. The installation area of ​​the semiconductor device in the product is increased, and there are many limitations in practical applications. Contents of the invention [0003] Aiming at the above problems, the present invention provides a three-dimensional multi-chip parallel structure that increases the overcurrent capability of devices without increasing the installation area. [0004] The technical solution of the present invention is: a three-dimensional mul...

Claims

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Application Information

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IPC IPC(8): H01L25/07
CPCH01L25/074
Inventor 周理明薛伟吕强肖宝童金铭熊鹏程王毅
Owner YANGZHOU YANGJIE ELECTRONIC TECH CO LTD