Three-dimensional multi-chip parallel packaging structure
A multi-chip, parallel technology, applied in electrical components, electrical solid devices, circuits, etc., can solve the problem of increasing the installation area of semiconductor devices, and achieve the effect of reducing the installation area
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[0017] Combine the following Figure 1-3 Further explain the present invention, including frame 1, chip 2 and jumper wire 3, the frame includes frame A11 and frame B12, and chip layer 1, chip layer 2 ... chip layer n, n are stacked on the frame B12 from bottom to top in sequence ≥2; the polarities of the opposite faces of adjacent chip layers are the same,
[0018] A jumper wire Ak connecting the frame A is provided on the top surface of the odd-numbered layer of the chip layer, and k is 1, 3, 5...n;
[0019] A jumper Bj connecting the frame B is provided on the top surface of the even-numbered layer of the chip layer; j is 2, 4, 6...n;
[0020] The sum of the jumper Ak and the jumper Bj is consistent with the layer number of the chip layer. n is a numerical serial number.
[0021] Each chip layer is stacked with m chip monomers according to the form of serial connection, m≥1. m is the quantity number.
[0022] The tin layer 4 used for connection between the frame 1, the ...
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