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A Realization Method of Two-Dimensional Ordered Statistical Constant False Alarm Detector Based on FPGA

An implementation method and detector technology, applied in the direction of instruments, measurement devices, radio wave measurement systems, etc., can solve the problems of increasing detection delay and affecting the real-time performance of target detection and detection, so as to achieve low detection delay and save BRAM resource consumption , The effect of conveniently locating the position of the reference unit

Active Publication Date: 2022-05-17
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] When using hardware to implement, when the two-dimensional power matrix is ​​too large, the traditional reordering and comparison of cached data will increase the consumption of hardware storage resources, and repeated reading and writing of memory data will increase the detection delay and affect the real-time performance of target detection.

Method used

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  • A Realization Method of Two-Dimensional Ordered Statistical Constant False Alarm Detector Based on FPGA
  • A Realization Method of Two-Dimensional Ordered Statistical Constant False Alarm Detector Based on FPGA
  • A Realization Method of Two-Dimensional Ordered Statistical Constant False Alarm Detector Based on FPGA

Examples

Experimental program
Comparison scheme
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Embodiment

[0070] This example includes the following steps:

[0071] Step 1: Set the shift register bank according to the size of the two-dimensional matrix.

[0072] It is assumed that after the radar echo data passes through MTI and MTD, the size of the two-dimensional power matrix obtained is 30×512. It represents the Doppler dimension unit M=30, and the distance dimension unit L=512.

[0073] Set the distance dimension sliding window length to X=21, the Doppler dimension sliding window length Y=21, the left, right, upper and lower reference units of the reference units are all 8, the number of protection units is 2, and the detection unit is in the middle. False alarm probability is 10e-4, threshold factor coefficient α r = α d = 10.8.

[0074] Program in Verilog language, and use the for statement to call the array to form a register group. The number of register groups is 21, the number of registers in each register group is 30, and the register data bit width is set to 16 bi...

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Abstract

The invention relates to the technical field of radar target detection, and in particular relates to a method for realizing an FPGA-based two-dimensional ordered statistical constant false alarm detector. The method of the invention starts from the input of the two-dimensional power matrix, and detects every clock cycle, reduces the time delay of repeated reading of the data cache, and can effectively improve the detection speed. In view of the large amount of calculation in the traditional OS-CFAR (Ordered Statistical Constant False Alarm) sorting process, the parallel comparison is used to complete the FPGA implementation method to reduce the complexity of sorting. Fully considering the reusability of the module, the two-dimensional sliding window structure setting is completed through the shift register group to realize the two-dimensional OS-CFAR detection, which can save the BRAM memory resources and DSP resources of the FPGA.

Description

technical field [0001] The invention belongs to the technical field of radar target detection, and in particular relates to an FPGA-based two-dimensional ordered statistical constant false alarm detector implementation method. Background technique [0002] Radar target detection is commonly used in constant false alarm (CFAR) detection, and ordered statistical constant false alarm (OS-CFAR) detection, compared with unit average constant false alarm (CA-CFAR), has a stronger ability to interfere with multiple targets and can effectively suppress Interference with neighboring targets. When detecting a moving target, it is necessary to use the Doppler dimension information of the echo signal. After the echo signal is processed by down-conversion, sampling, pulse pressure, and coherent accumulation, a two-dimensional power matrix can be obtained. Target detection can be performed in range dimension and Doppler two-dimensional CFAR. [0003] The traditional two-dimensional dete...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01S13/50G01S13/04G01S13/06G01S7/41G01S7/35G01S7/292
CPCG01S13/50G01S13/04G01S13/06G01S7/418G01S7/292G01S7/354
Inventor 宗竹林罗杰
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA