Method and device for realizing 32-bit integer division with high precision and low time delay

Abstract

The invention provides a method and a device for realizing 32-bit integer division with high precision and low time delay. The method comprises the following steps: S1, if the dividend, the divisor and the input zero judgment unit are 0, directly outputting 0 and a zoom factor of 0 by a quotient; and S2, inputting the dividend and the divisor output by the step 1 into a symbol extraction module, and outputting the symbol of the quotient and the modulus values of the dividend and the divisor. In the present invention, an initial value of Newton iteration is realized by using a CORDIC with a relatively small number of iterations; addition-only and shift-only operations, resource consumption reduction, facilitating hardware implementation, scaling module, scaling the dividend divisor to the same amplitude position; the calculation bit width is reduced, the requirement for the number of iterations is reduced, the operation period is shortened, Newton iteration is added once, the operationprecision is improved at the cost of a small number of arithmetic units and time delay, the precision of the quotient is effectively guaranteed in the mode that the output result uses the quotient andthe scaling factor, the output bit width is small, and follow-up use is facilitated. Error less than one thousandth.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a method and device for realizing 32-bit integer division with high precision and low delay. Background technique [0002] In the field of digital signal processing, 32-bit integer dividers are often used, such as in signal normalization and channel estimation, but the existing 32-bit integer dividers have the following disadvantages: [0003] 1. Existing division schemes often use derivative division, SRT method, addition and subtraction alternate method, CORDIC method, etc. The operation cycle of these methods often increases a lot with the increase of the number of digits, which wastes power consumption. [0004] 2. With the increase of the data bit width, the middle bit width of the arithmetic unit often becomes larger and larger, occupying more storage space. [0005] 3. In order to ensure performance, the bit width of the output result is large, and the r...

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Problems solved by technology

[0003] 1. Existing division schemes often use derivative division, SRT method, addition and subtraction alternate method, CORDIC method, etc. The operation cycle of these methods often increases with the number of digits increasing, wasting power consumption

[0004] 2. With the increase of the data bit width, the middle bit width of the arithmetic unit is often larger and larger, occupying more storage space

[0005] 3. In order to ensure performance, the bit width of the output result is large, and the resource overhead of subsequent addition and multiplication is relatively large

[0006] 4. Reciprocal division, Newton iteration plus one multiplication is commonly used to realize a / b, but there are generally two sources of initial value of Newton iteration, look-up table method or Tylor expansion, both of which require storage space, and Tylor expansion Requires additional multiplication and addition, consuming resources

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