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Clock structure of field programmable gate array and adjusting method thereof

A technology of structure adjustment and gate array, applied in the field of FPGA, can solve the problems of inability to achieve performance, unstable clock, and inability of FPGA to reach the clock frequency.

Active Publication Date: 2020-10-27
SHANGHAI ANLOGIC INFOTECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, after greatly reducing the clock skew in the FPGA through a lot of efforts, those skilled in the art sometimes find that no matter how small the clock skew in the FPGA is reduced, strange clock instability may occur when the FPGA is running , making it impossible for the FPGA to achieve higher clock frequencies and hence higher performance

Method used

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  • Clock structure of field programmable gate array and adjusting method thereof
  • Clock structure of field programmable gate array and adjusting method thereof
  • Clock structure of field programmable gate array and adjusting method thereof

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Embodiment Construction

[0027] In the following description, many technical details are proposed in order to enable readers to better understand the application. However, those skilled in the art can understand that the technical solutions claimed in this application can be realized even without these technical details and various changes and modifications based on the following implementation modes.

[0028] Explanation of some concepts:

[0029] User trigger: refers to the trigger used by the user logic in the FPGA.

[0030] FPGA: Field Programmable Gate Array, Field Programmable Gate Array.

[0031] DFFs: D type flip-flop, D type flip-flop.

[0032] Serdes: Serializer-Deserializer, short for serializer and deserializer.

[0033] The following outlines some innovations in the implementation of the present application:

[0034] Prior to this application, those skilled in the art generally believed that clock skew was harmful, because clock skew would reduce operation efficiency and increase oper...

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Abstract

The invention relates to the technical field of FPGAs. The invention discloses a clock structure of a field programmable gate array and an adjusting method thereof. The method comprises the followingsteps that: user triggers and a clock network share the same power supply network; and at least one time delay component is arranged in the clock structure or the time delay of the at least one timedelay component in the clock structure is adjusted, so that the clock skew between the user triggers is increased, and the peak value of the voltage fluctuation of the power supply network caused by the simultaneous inversion of the user triggers is reduced.

Description

technical field [0001] The present application relates to the field of FPGA technology, in particular to related technologies of FPGA clock structure. Background technique [0002] With the development of process technology and application requirements, the scale of Field Programmable Gate Array (FPGA) is getting bigger and bigger, and the scale of clock tree is increasing accordingly, and correspondingly more logic works on the same clock. In order to achieve high-speed logic operation, try to optimize the clock tree so that the delay between the flip-flops (DFF) of each node on the clock tree is as balanced as possible, that is, the clock skew is as small as possible. [0003] For example, the Chinese patent application with application number 201811230885.9 mentioned that it is necessary to try to reduce the clock skew in FPGA. The application discloses in detail that in the FPGA programmable logic array, there are generally many clock networks (16-32) integrated, and th...

Claims

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Application Information

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IPC IPC(8): H03K19/0175
CPCH03K19/017581
Inventor 赵永胜蒙奕帆
Owner SHANGHAI ANLOGIC INFOTECH CO LTD