Soi field effect transistor with reduced side leakage and its preparation method

A field-effect transistor and main body technology, which is applied in the direction of transistor, semiconductor/solid-state device manufacturing, circuit, etc., can solve problems such as failure and leakage, and achieve the effect of reducing side leakage, reducing side leakage, and increasing leakage resistance

Active Publication Date: 2021-06-18
SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a SOI field effect transistor with reduced side leakage and a preparation method thereof, which is used to solve the problem that the SOI field effect transistor has a large total dose effect in the prior art. Amplitude response causes problems such as leakage or even failure

Method used

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  • Soi field effect transistor with reduced side leakage and its preparation method
  • Soi field effect transistor with reduced side leakage and its preparation method
  • Soi field effect transistor with reduced side leakage and its preparation method

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Experimental program
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Effect test

Embodiment 1

[0060] Such as figure 1 As shown, removing the insulating layer (BOX layer) below the channel of the SOI transistor can effectively prevent the total dose effect. This solution removes the insulating layer below the transistor channel to form a groove 101, which can effectively reduce the total dose effect. However, In the structure, the insulating layer (BOX layer) still has overlapping contact portion 102 with the conductive channel. When the total dose effect occurs, it will cause leakage in the direction of the dashed line.

[0061] Based on the above problems, such as Figure 2 to Figure 28 As shown, the present embodiment provides a method for preparing an SOI field effect transistor with reduced side leakage, and the method for preparing includes the steps of:

[0062] Such as Figure 2 to Figure 4 As shown, step 1) is first performed to provide a patterned SOI substrate 200, the patterned SOI substrate 200 includes a bottom substrate 201, an insulating layer 202 and...

Embodiment 2

[0088] This embodiment provides an SOI field effect transistor with reduced side leakage. The SOI field effect transistor with reduced side leakage can be prepared by the preparation method of the first embodiment above, but is not limited to the preparation method of the first embodiment, as long as it can be formed An SOI field effect transistor with reduced side leakage is sufficient. For the beneficial effect achieved by the SOI field effect transistor with reduced side leakage, please refer to Embodiment 1, which will not be repeated below.

[0089] Such as figure 2 , Figure 7 , Figure 25 to Figure 27 As shown, the SOI field effect transistor with reduced side leakage includes:

[0090] A patterned SOI substrate 200, the patterned SOI substrate 200 includes a bottom substrate 201, an insulating layer 202 and a top semiconductor layer 203, the insulating layer 202 below the top semiconductor layer 203 has a groove 204, the The groove 204 includes a main body groove ...

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Abstract

The invention provides an SOI field effect transistor with reduced side leakage and a preparation method thereof. The transistor comprises: a patterned SOI substrate having a bottom substrate, an insulating layer and a top semiconductor layer in the form of a semiconductor island, and the insulating layer has a concave The groove, the groove includes a main body groove extending along the second direction and at least one extended groove extending along the first direction and located at both ends of the main body groove and communicating with it; the semiconductor island completely covers the groove, and the semiconductor island includes a groove along the second direction. A first semiconductor layer extending in one direction and a second semiconductor layer extending in a second direction, the second semiconductor layer includes a second body semiconductor layer located above the body groove and a second extension semiconductor layer covering the extension groove; formed in A gate structure on the second semiconductor layer of the semiconductor island; a source region and a drain region formed at both ends of the first semiconductor layer. By providing the two ends of the main body groove with the extended groove connected thereto, the leakage resistance is effectively increased, and the side leakage of the groove is reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, and in particular relates to an SOI field effect transistor with reduced side leakage and a preparation method thereof. Background technique [0002] Field effect transistors on SOI substrates have good anti-single event effects, but because in the SOI structure, the insulating layer (BOX layer) tends to accumulate more positive charges when high-energy particles are incident, the positive charges are caused in the top silicon layer of SOI. The parasitic conductive channel is created, which introduces leakage current and makes the electrical performance of the device drift. This effect is called the total dose effect, and the total dose effect is the main reason for the failure of SOI transistors in the environment of high-energy particle irradiation. Contents of the invention [0003] In view of the shortcomings of the prior art described above, the purpose of the present i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L29/06H01L29/423H01L29/786
CPCH01L29/0638H01L29/0684H01L29/42376H01L29/4238H01L29/66742H01L29/78603H01L29/78609
Inventor 刘强俞文杰
Owner SHANGHAI INST OF MICROSYSTEM & INFORMATION TECH CHINESE ACAD OF SCI
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