Time-phased reliable watchdog circuit and control method thereof

Abstract

The invention discloses a time-phased reliable watchdog circuit and a control method thereof. On one hand, the time-phased reliable watchdog circuit provided by the invention comprises a processor anda watchdog in signal connection with the processor, and further comprises a synchronous output timer and a timer period configuration module; a timer overflow signal output end and a watchdog overtime signal output end of the synchronous output timer are respectively in signal connection with a three-state gate switch through a logic gate module to form a monitoring period switching control circuit; the synchronous signal output end of the synchronous output timer is connected with the enabling end of the three-state gate switch through a trigger holding circuit, and the output end of the three-state gate switch is connected with the reset end of the trigger holding circuit and the reset end of the watchdog. On the other hand, the invention provides a watchdog circuit control method whichis reliable in different time periods. According to the invention, the stability of a system circuit can be effectively enhanced, resources are saved, and the control flexibility is improved.

Description

technical field [0001] The invention belongs to the field of embedded electronic communication, and in particular relates to a time-divided reliable watchdog circuit, and also relates to a time-divided reliable watchdog circuit control method. Background technique [0002] In the embedded field, the stability of the processor usually requires peripheral circuit monitoring. Most of the methods are to add a watchdog circuit to the peripheral circuit of the processor in the circuit. Therefore, the watchdog timer is a peripheral device that is often used to detect whether the microprocessor is abnormal. After the watchdog timer is set, it periodically monitors the signal given by the microprocessor. If the watchdog does not receive The trigger signal given by the processor is considered to be abnormal in the working software or hardware of the microprocessor, and the microprocessor circuit is forced to reset after the timing time exceeds. [0003] At present, watchdogs are divi...

AI Technical Summary

Problems solved by technology

The timer has no synchronous output signal. In addition, when the first timer is reset and started, switching the first timer to the second timer also requires a state machine trigger to control the switch to output a reset signal. After that, the first timer It cannot continue to work before reset, so it is impossible to switch the first watchdog and the second watchdog before reset, so a new design is urgently needed to meet the needs of use

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