Multi-node multi-channel high-speed parallel processing method and system

Abstract

The invention provides a multi-node multi-channel high-speed parallel processing method and system, and the method comprises the steps: selecting one virtual channel from a plurality of virtual channels as a target virtual channel based on the task demands of a to-be-processed data package, determining a corresponding host forward buffer area and a corresponding host reverse buffer area as targetbuffer areas based on the target virtual channel; distributing required forward memory nodes and reverse memory nodes for the to-be-processed data packet from the target buffer area, writing the to-be-processed data packet into the distributed forward memory nodes in the m forward memory nodes by the host, and writing a command word into the corresponding command word FIFO; and when the forward DMA module polls the command word FIFO, the forward DMA module determines the address information of the allocated forward memory node and the length of the to-be-processed data packet based on the command word information, and transmits the to-be-processed data packet to the algorithm module and the like. According to the invention, high-speed transmission and high-speed processing of data can be realized.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a multi-node and multi-channel high-speed parallel processing method and system. Background technique [0002] FPGA (Field-Programmable Gate Array), that is, field programmable gate array, it is in PAL (Programmable Array Logic) programmable array logic, GAL (Generic Array Logic) general array logic, CPLD (Complex Programmable Logic Device) complex programmable The product of further development on the basis of programmable devices such as logic devices. It appeared as a semi-custom circuit in the field of application-specific integrated circuits, which not only solved the shortcomings of custom circuits, but also overcome the shortcomings of the limited number of original programmable device gates. [0003] At present, the main control functions of the encryption card are integrated in the FPGA. When the data on the host needs to be sent to the encryption card for encryption ...

AI Technical Summary

Problems solved by technology

If the data that needs to be encrypted and decrypted is sent and received in one channel, once the amount of data becomes large, the single-channel mode is likely to cause data congestion.

In addition, if there is a large amount of task data occupying the front end of the data stream, the data of other tasks can only be transmitted after the task data is completed, which will easily cause some processing units in the FPGA to be idle, and the resource utilization rate is not high

In some scenarios, a task may need to encrypt and decrypt a set of ordered data packets. Since the sizes of each data packet may be different, the time spent on encryption and decryption of each data packet may vary, which may easily lead to a set of After the encrypted and decrypted data packets are out of order, it is difficult to solve the problem of data packet sorting by using the traditional single-channel mode

[0004] In addition, if multiple tasks of the same type need to be processed based on the same channel in the same period of time, if there is a task data that occupies the task processing channel, other task data that needs to be processed, especially urgent task data, must wait for the upload. The current task data can only be sent after a task data is processed; if the previous task has a large amount of data, the task processing channel will be occupied for a long time, causing other task data congestion; that is, this task processing method will inevitably affect other needs. The transmission efficiency and processing progress of the processed task data, especially the urgent task data, lead to low processing efficiency of the system

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